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<p>This paper presents the design of positive feedback source coupled logic (PFSCL) registers for mixed-signal applications. The paper proposes static and dynamic PFSCL registers design. The two static register (SR-1, SR-2) designs involves feedback connection and employs PFSCL fundamental cells (SR-1) and PFSCL tri-state buffers (SR-2). The proposed dynamic PFSCL register (DR) avoids the feedback connection and simultaneously lowers the overall power consumption. The paper is extended for the design of clock skew insensitive register by addressing the clock overlap issue. All the proposed PFSCL registers are simulated in LTspice using PTM 90&#xa0;nm CMOS technology parameters and the layouts are drawn in the microwind tool. The performance of the proposed registers has been compared with conventional CMOS registers. It is observed that proposed DR achieves maximum improvements across all key performance parameters. A maximum reduction of 94.45%, 77.6%, 86.25%, 85%, 78.5% in CLK to Q, D to Q propagation delay, power, setup and hold time respectively at the cost of 48% increased. Also, the Monte Carlo and corner simulation results reveals that proposed dynamic register design exhibits the lowest variations in both CLK-Q and D-Q propagation delay. Finally, a serial in serial out shift register implementation is included as a design example.</p>

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Register design in positive feedback source coupled logic for mixed-signal applications

  • 期刊论文

  • 发表日期：

    2025年7月15日

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  • Shikha,
  • Kirti Gupta,
  • Neeta Pandey

摘要

This paper presents the design of positive feedback source coupled logic (PFSCL) registers for mixed-signal applications. The paper proposes static and dynamic PFSCL registers design. The two static register (SR-1, SR-2) designs involves feedback connection and employs PFSCL fundamental cells (SR-1) and PFSCL tri-state buffers (SR-2). The proposed dynamic PFSCL register (DR) avoids the feedback connection and simultaneously lowers the overall power consumption. The paper is extended for the design of clock skew insensitive register by addressing the clock overlap issue. All the proposed PFSCL registers are simulated in LTspice using PTM 90 nm CMOS technology parameters and the layouts are drawn in the microwind tool. The performance of the proposed registers has been compared with conventional CMOS registers. It is observed that proposed DR achieves maximum improvements across all key performance parameters. A maximum reduction of 94.45%, 77.6%, 86.25%, 85%, 78.5% in CLK to Q, D to Q propagation delay, power, setup and hold time respectively at the cost of 48% increased. Also, the Monte Carlo and corner simulation results reveals that proposed dynamic register design exhibits the lowest variations in both CLK-Q and D-Q propagation delay. Finally, a serial in serial out shift register implementation is included as a design example.