<p>In this paper, we utilize the advantages of Molybdenum Disulfide (MoS<InlineEquation ID="IEq2"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="10470_2025_2457_Article_IEq1.gif" Format="GIF" Height="10" Rendition="HTML" Resolution="72" Type="Linedraw" Width="8" /> </InlineMediaObject> <EquationSource Format="TEX">\({}_2\)</EquationSource> </InlineEquation>) transistors to design a Flash analog-to-digital converter (ADC) that achieves a reduced active area and dynamic power. MoS<InlineEquation ID="IEq3"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="10470_2025_2457_Article_IEq1.gif" Format="GIF" Height="10" Rendition="HTML" Resolution="72" Type="Linedraw" Width="8" /> </InlineMediaObject> <EquationSource Format="TEX">\({}_2\)</EquationSource> </InlineEquation> field-effect transistors (FETs) are a class of emerging devices based on two-dimensional (2D) materials, offering high ON/OFF current ratios, excellent electrostatic control, and scalability, making them suitable for next-generation low-power electronics. To eliminate static power dissipation, the proposed ADC incorporates the threshold inverter quantization (TIQ) technique. A SPICE-compatible charge-based model for MoS<InlineEquation ID="IEq4"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="10470_2025_2457_Article_IEq1.gif" Format="GIF" Height="10" Rendition="HTML" Resolution="72" Type="Linedraw" Width="8" /> </InlineMediaObject> <EquationSource Format="TEX">\({}_2\)</EquationSource> </InlineEquation> transistor, published in the literature, is used to simulate the proposed ADC. Due to their high ON/OFF current ratio and nanoscale geometry, MoS<InlineEquation ID="IEq5"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="10470_2025_2457_Article_IEq1.gif" Format="GIF" Height="10" Rendition="HTML" Resolution="72" Type="Linedraw" Width="8" /> </InlineMediaObject> <EquationSource Format="TEX">\({}_2\)</EquationSource> </InlineEquation> FETs enable significant reductions in ADC active area and dynamic power relative to traditional device technologies. Simulation results reveal that the differential nonlinearity (DNL) ranges of [-0.18, 0.12]LSB , and the integral nonlinearity (INL) ranges of [-0.32, 0.24]LSB, both satisfying the requirements for 4-bit resolution at a 2 V operating voltage. In addition, the low ADC active area of 3050 <InlineEquation ID="IEq6"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="10470_2025_2457_Article_IEq6.gif" Format="GIF" Height="19" Rendition="HTML" Resolution="72" Type="Linedraw" Width="33" /> </InlineMediaObject> <EquationSource Format="TEX">\(\mu m^2\)</EquationSource> </InlineEquation> rendering it well-suited for implementation in very large-scale integration (VLSI) circuits. Variations in process, temperature, and supply voltage affect the proposed method, and their influence on ADC performance is analyzed.</p>

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Energy-Efficient flash ADC architecture based on MoS\({}_2\) transistors

  • Ashkan Horri

摘要

In this paper, we utilize the advantages of Molybdenum Disulfide (MoS \({}_2\) ) transistors to design a Flash analog-to-digital converter (ADC) that achieves a reduced active area and dynamic power. MoS \({}_2\) field-effect transistors (FETs) are a class of emerging devices based on two-dimensional (2D) materials, offering high ON/OFF current ratios, excellent electrostatic control, and scalability, making them suitable for next-generation low-power electronics. To eliminate static power dissipation, the proposed ADC incorporates the threshold inverter quantization (TIQ) technique. A SPICE-compatible charge-based model for MoS \({}_2\) transistor, published in the literature, is used to simulate the proposed ADC. Due to their high ON/OFF current ratio and nanoscale geometry, MoS \({}_2\) FETs enable significant reductions in ADC active area and dynamic power relative to traditional device technologies. Simulation results reveal that the differential nonlinearity (DNL) ranges of [-0.18, 0.12]LSB , and the integral nonlinearity (INL) ranges of [-0.32, 0.24]LSB, both satisfying the requirements for 4-bit resolution at a 2 V operating voltage. In addition, the low ADC active area of 3050 \(\mu m^2\) rendering it well-suited for implementation in very large-scale integration (VLSI) circuits. Variations in process, temperature, and supply voltage affect the proposed method, and their influence on ADC performance is analyzed.