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<p>This paper presents a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an RC hybrid digital-to-analog converter (DAC) and auto-zero (AZ) comparator. To reduce the circuit area and to achieve the high linearity, we propose the use of an RC hybrid DAC inside an SAR ADC. The resistor array is arranged in the least significant bit (LSB) ladder, and the capacitor array is arranged in the most significant bit (MSB) ladder. Placing RDAC instead of CDAC in a 4-bit LSB ladder can reduce the total capacitance area. To reduce the offset and low-frequency noise, various AZ techniques are widely adopted for the comparator, however, the offset storage capacitor is placed in serial to the signal path, the signal charges in CDAC or offset storage capacitors can be distorted. In this design, an autozeroed pre-amplifier is designed using a fully differential difference amplifier (FDDA) and feedback offset sampling to prevent the charge distortion during the AZ operation. The proposed SAR ADC is implemented using a standard 0.18&#xa0;μm CMOS process. The simulated and measured effective number of bits (ENOB) of this SAR ADC are 9.98-bit and 9.56-bit, respectively. The linearity performance of the proposed SAR ADC was measured with DNL having a maximum of 0.28 LSB and a minimum of -0.18 LSB, while INL had a maximum of 0.5 LSB and a minimum of -0.19 LSB. And the proposed SAR ADC’s total current consumption is 41.4 µA with a 1.8&#xa0;V power supply.</p>

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Low-noise 10-bit SAR ADC with auto-zero comparator using fully differential difference amplifier

  • 期刊论文

  • 发表日期：

    2025年6月28日

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  • Hyeoktae Son,
  • Mookyoung Yoo,
  • Sanggyun Kang,
  • Byeongkwan Jin,
  • Kyounghwan Kim,
  • Jihyang Wi,
  • Gibae Nam,
  • Seungmin Ahn,
  • Hyoungho Ko

摘要

This paper presents a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an RC hybrid digital-to-analog converter (DAC) and auto-zero (AZ) comparator. To reduce the circuit area and to achieve the high linearity, we propose the use of an RC hybrid DAC inside an SAR ADC. The resistor array is arranged in the least significant bit (LSB) ladder, and the capacitor array is arranged in the most significant bit (MSB) ladder. Placing RDAC instead of CDAC in a 4-bit LSB ladder can reduce the total capacitance area. To reduce the offset and low-frequency noise, various AZ techniques are widely adopted for the comparator, however, the offset storage capacitor is placed in serial to the signal path, the signal charges in CDAC or offset storage capacitors can be distorted. In this design, an autozeroed pre-amplifier is designed using a fully differential difference amplifier (FDDA) and feedback offset sampling to prevent the charge distortion during the AZ operation. The proposed SAR ADC is implemented using a standard 0.18 μm CMOS process. The simulated and measured effective number of bits (ENOB) of this SAR ADC are 9.98-bit and 9.56-bit, respectively. The linearity performance of the proposed SAR ADC was measured with DNL having a maximum of 0.28 LSB and a minimum of -0.18 LSB, while INL had a maximum of 0.5 LSB and a minimum of -0.19 LSB. And the proposed SAR ADC’s total current consumption is 41.4 µA with a 1.8 V power supply.