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<p>This paper proposes a subthreshold CMOS voltage reference circuit. The design comprises a start-up circuit, a bias current generator, and a voltage subtraction output stage. Fabricated in a 0.18&#xa0;µm CMOS process, the circuit achieves a power consumption of 17&#xa0;nW at 27&#xa0;°C with a supply voltage ranging from 1 to 3&#xa0;V. At <i>V</i><sub>DD</sub> = 1.8&#xa0;V, the output reference voltage (<i>V</i><sub>REF</sub>) is 297.3&#xa0;mV, exhibiting a temperature coefficient (TC) of 2.565&#xa0;ppm/°C over a temperature range of from − 40 to 125&#xa0;°C. The power supply ripple rejection ratio (PSRR) at 10&#xa0;Hz is − 102.9&#xa0;dB. The proposed architecture demonstrates advantages in low-power consumption, compact area, and stable output performance.</p>

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A subthreshold CMOS voltage reference with low temperature coefficient, low power and high PSRR

  • 期刊论文

  • 发表日期：

    2025年5月21日

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  • Shubing Wan,
  • Hua Wu,
  • Jiawei Cheng,
  • Xianguo Cao

摘要

This paper proposes a subthreshold CMOS voltage reference circuit. The design comprises a start-up circuit, a bias current generator, and a voltage subtraction output stage. Fabricated in a 0.18 µm CMOS process, the circuit achieves a power consumption of 17 nW at 27 °C with a supply voltage ranging from 1 to 3 V. At VDD = 1.8 V, the output reference voltage (VREF) is 297.3 mV, exhibiting a temperature coefficient (TC) of 2.565 ppm/°C over a temperature range of from − 40 to 125 °C. The power supply ripple rejection ratio (PSRR) at 10 Hz is − 102.9 dB. The proposed architecture demonstrates advantages in low-power consumption, compact area, and stable output performance.