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<p>This paper introduces a block that has the potential to create a controllable zero and pole. This block can be a very good candidate for two- and three-stage compensation methods. These topologies have the capability of optimizing multistage CMOS amplifiers and driving large capacitive loads. Departing from traditional cascading techniques, this approach utilizes an active capacitor to generate controllable zeros and poles, maintaining amplifier gain while achieving a wider bandwidth. The method proves effective in two-stage amplifiers, showcasing superior performance in compensating large capacitors with minimal impact on bandwidth. Extending the approach to three-stage amplifiers, the proposed topology removes non-dominant poles, resulting in enhanced stability and performance. Simulations across process corners affirm the robustness of the proposed method, making it a promising solution for low-power, large-capacitive-load amplifier designs. The proposed compensation method achieves a slew rate (SR) of 1&#xa0;V/µs and a gain bandwidth product (GBW) of 1.8&#xa0;MHz while driving a 10&#xa0;nF load. This outstanding performance further accentuates the adaptability of the proposed compensation method, solidifying its potential in addressing the evolving demands of contemporary amplifier designs.</p>

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Improved performance of two-and three-stage amplifiers with zero-and pole-block creator

  • 期刊论文

  • 发表日期：

    2025年5月15日

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  • Zohreh Mohamadi,
  • Behzad Ghanavati,
  • Jabbar Ganji,
  • Seyyed Sajjad Tabatabaee

摘要

This paper introduces a block that has the potential to create a controllable zero and pole. This block can be a very good candidate for two- and three-stage compensation methods. These topologies have the capability of optimizing multistage CMOS amplifiers and driving large capacitive loads. Departing from traditional cascading techniques, this approach utilizes an active capacitor to generate controllable zeros and poles, maintaining amplifier gain while achieving a wider bandwidth. The method proves effective in two-stage amplifiers, showcasing superior performance in compensating large capacitors with minimal impact on bandwidth. Extending the approach to three-stage amplifiers, the proposed topology removes non-dominant poles, resulting in enhanced stability and performance. Simulations across process corners affirm the robustness of the proposed method, making it a promising solution for low-power, large-capacitive-load amplifier designs. The proposed compensation method achieves a slew rate (SR) of 1 V/µs and a gain bandwidth product (GBW) of 1.8 MHz while driving a 10 nF load. This outstanding performance further accentuates the adaptability of the proposed compensation method, solidifying its potential in addressing the evolving demands of contemporary amplifier designs.