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<p>In this paper a low voltage low power FGMOS based cascode current mirror is proposed. The use of FGMOS transistor improves the performance of the proposed current mirror in terms of output impedance, current accuracy, power consumption and input/output voltage requirements. The circuit has power consumption of 16.2&#xa0;μW, the input and output voltage requirement 0.24&#xa0;V and 0.14&#xa0;V and output impedance of 27.92&#xa0;GΩ. In order to assess the robustness of the proposed current mirror, the circuit has been simulated under various conditions, including different process corners, variations in supply voltage, and temperature changes (PVT variations). The Monte-Carlo analysis has also been done to further validate the robustness of the proposed current mirror. Additionally; to analyse the linearity of the proposed current mirror, total harmonic distortion (THD) has been simulated. The layout of the proposed circuit has been incorporated, along with post-layout simulations. To confirm the validity of the proposed current mirror it has been used to design current mode full wave rectifier. All the simulations have been done using SPICE 180&#xa0;nm CMOS technology parameters.</p>

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Low voltage low power FGMOS based current mirror with improved performance

  • 期刊论文

  • 发表日期：

    2025年4月28日

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  • Akshdeep Kumar,
  • Rakshit Srivastava,
  • Richa Srivastava,
  • Garima Varshney,
  • Pravesh

摘要

In this paper a low voltage low power FGMOS based cascode current mirror is proposed. The use of FGMOS transistor improves the performance of the proposed current mirror in terms of output impedance, current accuracy, power consumption and input/output voltage requirements. The circuit has power consumption of 16.2 μW, the input and output voltage requirement 0.24 V and 0.14 V and output impedance of 27.92 GΩ. In order to assess the robustness of the proposed current mirror, the circuit has been simulated under various conditions, including different process corners, variations in supply voltage, and temperature changes (PVT variations). The Monte-Carlo analysis has also been done to further validate the robustness of the proposed current mirror. Additionally; to analyse the linearity of the proposed current mirror, total harmonic distortion (THD) has been simulated. The layout of the proposed circuit has been incorporated, along with post-layout simulations. To confirm the validity of the proposed current mirror it has been used to design current mode full wave rectifier. All the simulations have been done using SPICE 180 nm CMOS technology parameters.