Scholarlink

<p>With the rapid growth of data traffic, there is an increasing demand for larger bandwidths in fixed networks. The transmitter bandwidth extension is usually achieved by combining analog multiplexers (AMUX) with digital-to-analog converters (DAC) designed in CMOS. Additionally, feedforward equalization (FFE) is incorporated at the high-speed front-end. However, this adds complexity and significant power consumption. In this work, we describe an alternative FFE approach that reduces the complexity of power-hungry high-speed front-ends, thereby improving power efficiency. This approach uses a 28 nm CMOS chip that sends two outputs with FFE predistorted data at 40/80 Gbps NRZ/PAM4. When combined with an AMUX, it generates equalized eye diagrams at 80/160 Gbps NRZ/PAM4 after a channel model with an insertion loss of 8.4 dB at 40 GHz, with a voltage swing of 100&#xa0;mVpp,diff/190&#xa0;mVpp,diff, while dissipating 0.889&#xa0;W of power (5.56 pJ/bit).</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

A 2-way interleaving 3-tap analog feedforward equalization for high-speed analog multiplexing

  • 期刊论文

  • 发表日期：

    2025年4月23日

查看全文
  • Thomas Gorzka,
  • Mark Ingels,
  • Xin Wang,
  • Joris Van Kerrebrouck,
  • Nishant Singh,
  • Guy Torfs,
  • Johan Bauwelinck,
  • Jan Craninckx,
  • Piet Wambacq

摘要

With the rapid growth of data traffic, there is an increasing demand for larger bandwidths in fixed networks. The transmitter bandwidth extension is usually achieved by combining analog multiplexers (AMUX) with digital-to-analog converters (DAC) designed in CMOS. Additionally, feedforward equalization (FFE) is incorporated at the high-speed front-end. However, this adds complexity and significant power consumption. In this work, we describe an alternative FFE approach that reduces the complexity of power-hungry high-speed front-ends, thereby improving power efficiency. This approach uses a 28 nm CMOS chip that sends two outputs with FFE predistorted data at 40/80 Gbps NRZ/PAM4. When combined with an AMUX, it generates equalized eye diagrams at 80/160 Gbps NRZ/PAM4 after a channel model with an insertion loss of 8.4 dB at 40 GHz, with a voltage swing of 100 mVpp,diff/190 mVpp,diff, while dissipating 0.889 W of power (5.56 pJ/bit).