Scholarlink

<p>This paper presents an enhanced N-path filter architecture addressing the fundamental limitations of conventional designs in wireless communication systems. The proposed solution tackles two critical challenges: insufficient harmonic rejection and signal loss. By integrating a high-gain low-noise amplifier (LNA) at the input stage and implementing a novel transconductance amplifier-based weighted sinusoidal signal fitting technique, the filter achieves superior performance metrics. Implemented in SMIC 180&#xa0;nm CMOS technology, the design demonstrates frequency tunability from 800&#xa0;MHz to 1.2&#xa0;GHz. Simulation results show third and fifth harmonic rejection ratios of 61&#xa0;dB and 67&#xa0;dB, respectively. The filter exhibits a gain of 21&#xa0;dB with a noise figure of 8–9&#xa0;dB and an IIP3 of <InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="10470_2025_2374_Article_IEq1.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="19" /> </InlineMediaObject> <EquationSource Format="TEX">\(-\)</EquationSource> <EquationSource Format="MATHML"><math> <mo>-</mo> </math></EquationSource> </InlineEquation>6.2&#xa0;dBm. These results represent a significant advancement over traditional N-path filter implementations, offering promising prospects for practical wireless applications.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Design of a high-gain N-path filter with harmonic rejection

  • 期刊论文

  • 发表日期：

    2025年3月21日

查看全文
  • Shuxiang Song,
  • Changping Liu,
  • Pinqun Jiang,
  • Mingcan Cen

摘要

This paper presents an enhanced N-path filter architecture addressing the fundamental limitations of conventional designs in wireless communication systems. The proposed solution tackles two critical challenges: insufficient harmonic rejection and signal loss. By integrating a high-gain low-noise amplifier (LNA) at the input stage and implementing a novel transconductance amplifier-based weighted sinusoidal signal fitting technique, the filter achieves superior performance metrics. Implemented in SMIC 180 nm CMOS technology, the design demonstrates frequency tunability from 800 MHz to 1.2 GHz. Simulation results show third and fifth harmonic rejection ratios of 61 dB and 67 dB, respectively. The filter exhibits a gain of 21 dB with a noise figure of 8–9 dB and an IIP3 of \(-\) - 6.2 dBm. These results represent a significant advancement over traditional N-path filter implementations, offering promising prospects for practical wireless applications.