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<p>In this study, a novel low-power, high-speed hybrid architecture for a 16-bit carry look-ahead adder (CLA) employing 4:2 compressors is proposed. To enhance compressor latency and power efficiency, a new hybrid full adder architecture based on eleven transistors is implemented. The conventional CMOS (CCMOS) architecture of CLAs is hindered by poor latency due to the significant parasitic capacitance presented by higher-order carry generation modules, unlike the ripple carry adder architecture. To mitigate latency issues in the CLA architecture, the design generates odd and even carry bits independently. The proposed 16-bit CLA architecture is simulated using a 45&#xa0;nm PTM technology model with the Mentor Graphics Tanner EDA tool. Comprehensive simulation-based analyses and comparisons with state-of-the-art methodologies are conducted, focusing on power consumption, delay, and area (transistor count). The proposed design has a power-delay product of 108 femtojoules, which is 53% better than the CCMOS 16-bit CLA architecture.</p>

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A novel low-power, high-speed carry look ahead adder utilizing 11-T hybrid full adder module based 4:2 compressor unit for low-power applications

  • 期刊论文

  • 发表日期：

    2025年3月18日

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  • Nimai Halder,
  • Biswarup Mukherjee

摘要

In this study, a novel low-power, high-speed hybrid architecture for a 16-bit carry look-ahead adder (CLA) employing 4:2 compressors is proposed. To enhance compressor latency and power efficiency, a new hybrid full adder architecture based on eleven transistors is implemented. The conventional CMOS (CCMOS) architecture of CLAs is hindered by poor latency due to the significant parasitic capacitance presented by higher-order carry generation modules, unlike the ripple carry adder architecture. To mitigate latency issues in the CLA architecture, the design generates odd and even carry bits independently. The proposed 16-bit CLA architecture is simulated using a 45 nm PTM technology model with the Mentor Graphics Tanner EDA tool. Comprehensive simulation-based analyses and comparisons with state-of-the-art methodologies are conducted, focusing on power consumption, delay, and area (transistor count). The proposed design has a power-delay product of 108 femtojoules, which is 53% better than the CCMOS 16-bit CLA architecture.