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<p>A level-crossing ADC, which includes a 1-bit DAC, a rail-to-rail continuous-time comparator and a 3-stage continuous-time comparator, has been simulated in 0.18&#xa0;μm CMOS process with 0.8&#xa0;V supply voltage. Interpolation between samples has been used to add more samples to the original signal and reconstruct ADC’s output signal. The ADC has SNDR of 47.2 dB (with polynomial interpolation), ENOB of 7.5-bit and power consumption of 460 nW for 1&#xa0;kHz sinusoidal input signal with common-mode voltage of 400 mV and amplitude of 800&#xa0;m<InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="10470_2025_2344_Article_IEq1.gif" Format="GIF" Height="16" Rendition="HTML" Resolution="72" Type="Linedraw" Width="30" /> </InlineMediaObject> <EquationSource Format="TEX">\(\:{\text{V}}_{\text{P}\text{P}}\)</EquationSource> </InlineEquation>.</p>

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On the design of a level-crossing ADC with 1-bit DAC and rail-to-rail continuous-time comparator

  • 期刊论文

  • 发表日期：

    2025年2月8日

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  • Fereshte Shahbazi,
  • Hossein Shamsi

摘要

A level-crossing ADC, which includes a 1-bit DAC, a rail-to-rail continuous-time comparator and a 3-stage continuous-time comparator, has been simulated in 0.18 μm CMOS process with 0.8 V supply voltage. Interpolation between samples has been used to add more samples to the original signal and reconstruct ADC’s output signal. The ADC has SNDR of 47.2 dB (with polynomial interpolation), ENOB of 7.5-bit and power consumption of 460 nW for 1 kHz sinusoidal input signal with common-mode voltage of 400 mV and amplitude of 800 m \(\:{\text{V}}_{\text{P}\text{P}}\) .