<p>FPGA bitstream is a binary file containing chip configuration information. It is often compressed to conserve storage space and reduce configuration time. However, if the bitstream file is compressed, hardware attacks cannot be detected because FPGA reverse-engineering tools can only decompile uncompressed and unencrypted bitstream. This study proposes a low complexity decompression method for commercial FPGA bitstreams, which is a crucial step for assessing the security of FPGAs. By comparing the structure of compressed and uncompressed bitstream files, we identify the compression region, extract the compressed data, and construct a database for the mapping information. Then, we introduce a decoding algorithm that utilizes a sliding window approach based on the characteristics of the compressed data and implement the algorithm on an Intel Cyclone V FPGA. Finally, the proposed framework is validated on 24 different types of Intel FPGAs from 6 families, with a perfect accuracy rate of 100%. To the best of our knowledge, this is the first paper to disclose a decompression method for commercial FPGAs.</p>

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Low complexity decompression method for FPGA bitstreams

  • Lingrui Ren,
  • Xingcan Zhang,
  • Jian Wang

摘要

FPGA bitstream is a binary file containing chip configuration information. It is often compressed to conserve storage space and reduce configuration time. However, if the bitstream file is compressed, hardware attacks cannot be detected because FPGA reverse-engineering tools can only decompile uncompressed and unencrypted bitstream. This study proposes a low complexity decompression method for commercial FPGA bitstreams, which is a crucial step for assessing the security of FPGAs. By comparing the structure of compressed and uncompressed bitstream files, we identify the compression region, extract the compressed data, and construct a database for the mapping information. Then, we introduce a decoding algorithm that utilizes a sliding window approach based on the characteristics of the compressed data and implement the algorithm on an Intel Cyclone V FPGA. Finally, the proposed framework is validated on 24 different types of Intel FPGAs from 6 families, with a perfect accuracy rate of 100%. To the best of our knowledge, this is the first paper to disclose a decompression method for commercial FPGAs.