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<p>Real-time cardiac MRI (RT-CMRI) provides dynamic imaging of the heart throughout the cardiac cycle, offering critical insights into heart function. Continuous imaging demands high frame rates and precise reconstructions, offering significant challenges in balancing speed and accuracy for clinical viability. The generalized auto-calibrating partial parallel acquisition (GRAPPA) is a widely used parallel MRI method. However, multiple receiver coils in GRAPPA significantly increase the computational demands, prolonging reconstruction times. Field programmable gate array (FPGA)-based implementations offer a promising approach to address GRAPPA’s computational demands in RT-CMRI. However, challenges exist due to limited on-chip memory and computational resources especially for a large number of receiver coils. This paper presents a novel system-on-chip-based accelerator to address the computational challenges of RT-CMRI on FPGA devices. The proposed accelerator features a unique capability to compress large calibration equations in the GRAPPA, reducing data processing and storage requirements. Implemented on the AMD® Zynq™ Ultrascale + platform, the proposed architecture features an on-chip ARM® Cortex®-A53 processor that manages data flow between the accelerator and a DDR4 memory unit. The proposed accelerator is validated through GRAPPA reconstruction using 18-coil and 30-coil in-vivo cardiac MRI datasets. Reconstruction quality is quantified using signal-to-noise ratio and root mean square error. The reconstruction results demonstrate significant improvements, with speed-up factors of up to ~ 181× and ~ 9× over contemporary CPU and GPU-based GRAPPA reconstruction methods, respectively. The proposed architecture reconstructs CMRI data with up to 30 channels at frame rates exceeding 26 frames/sec, without compromising the reconstruction quality. </p>

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System-on-Chip Based Accelerator Design for Real-Time Cardiac MRI: Balancing Speed and Accuracy

  • 期刊论文

  • 发表日期：

    2025年7月28日

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  • Yumna Bilal,
  • Omair Inam,
  • Abdul Basit,
  • Muhammad Faisal Siddiqui,
  • Hammad Omer

摘要

Real-time cardiac MRI (RT-CMRI) provides dynamic imaging of the heart throughout the cardiac cycle, offering critical insights into heart function. Continuous imaging demands high frame rates and precise reconstructions, offering significant challenges in balancing speed and accuracy for clinical viability. The generalized auto-calibrating partial parallel acquisition (GRAPPA) is a widely used parallel MRI method. However, multiple receiver coils in GRAPPA significantly increase the computational demands, prolonging reconstruction times. Field programmable gate array (FPGA)-based implementations offer a promising approach to address GRAPPA’s computational demands in RT-CMRI. However, challenges exist due to limited on-chip memory and computational resources especially for a large number of receiver coils. This paper presents a novel system-on-chip-based accelerator to address the computational challenges of RT-CMRI on FPGA devices. The proposed accelerator features a unique capability to compress large calibration equations in the GRAPPA, reducing data processing and storage requirements. Implemented on the AMD® Zynq™ Ultrascale + platform, the proposed architecture features an on-chip ARM® Cortex®-A53 processor that manages data flow between the accelerator and a DDR4 memory unit. The proposed accelerator is validated through GRAPPA reconstruction using 18-coil and 30-coil in-vivo cardiac MRI datasets. Reconstruction quality is quantified using signal-to-noise ratio and root mean square error. The reconstruction results demonstrate significant improvements, with speed-up factors of up to ~ 181× and ~ 9× over contemporary CPU and GPU-based GRAPPA reconstruction methods, respectively. The proposed architecture reconstructs CMRI data with up to 30 channels at frame rates exceeding 26 frames/sec, without compromising the reconstruction quality.