Energy-aware and latency-constrained NoC mapping in FPGA-enabled high performance distributed computing

The rapid development of components that were integrated into the single chip had a substantial influence on the NoC architecture performance metrics, including inter-core communication. Therefore, providing an efficient mapping among the cores that enhances communication between them is essential for overcoming such challenges. Throughput and latency can contribute significantly towards network performance improvement. This research presents HOME (Hybrid Optimization framework for Mapping of Energy-efficient and low-latency NoC), implemented on an FPGA platform to optimize core mapping and energy efficiency. The proposed framework utilizes a hybrid optimization strategy integrating Genetic Algorithm (GA), Simulated Annealing (SA), and Reinforcement Learning (RL) to enhance NoC performance. This research evaluated a set of real-time embedded applications, which reveals low latency on average of 11.2%, 9.8%, and 8.4% against MapGtoM algorithm, CSO Algorithm, and CURE Algorithm. The simulation time reduces at an average of 14.6%, 12.8% and 10.6% against MapGtoM algorithm, CSO Algorithm, and CURE Algorithm. The throughput increases at an average of 10.4%, 9.2% and 8.1% against MapGtoM algorithm, CSO Algorithm, and CURE Algorithm. The communication energy reduces at an average of 9.6%, 8.4% and 7.5% against MapGtoM algorithm, CSO Algorithm, and CURE Algorithm. The proposed algorithm was implemented and evaluated on the Xilinx Zynq XC7Z020-1CLG484-1L FPGA, which belongs to the Zynq 7000 series, using the Vivado 2024.1 design environment. The hardware results demonstrated improved performance over existing approaches, particularly in terms of delay and resource utilization.