<p>This research presents a comprehensive comparison of three prevalent latched-based sense amplifier architectures concerning delay and power consumption per bit. The study, conducted using 65&#xa0;nm technology, includes a 6&#xa0;T SRAM cell with minimal size and a 128-bit SRAM column to enhance simulation realism. One basic topology from each architecture is used for simulations. The outcomes reveal that the charge transfer sense amplifier exhibits superior performance in both delay and power consumption compared to its voltage mode and current mode counterparts. Supply and temperature sensitivity analyses further underscore the charge transfer sense amplifier's robust performance, particularly showcasing low delay variation with supply reduction, making it a favorable choice for subthreshold operation. Input sensitivity analysis indicates that the charge transfer sense amplifier outperforms in sensitivity, with lower offset compared to other architectures. Layout analysis reveals that, in our design, the CTSA consumes the largest area, requiring 16.8 μm² due to its higher transistor count, while the VMSA requires the least area, occupying only 8.1 μm² because of its simpler design and fewer transistors. These findings offer valuable insights for the design and implementation of sense amplifiers across diverse applications, emphasizing the potential advantages of the charge transfer sense amplifier in subthreshold and low-power scenarios.</p>