Scholarlink

<p>The integration of Schmitt trigger-based (ST) SRAM cell architecture, particularly into the design of the Single-Stacked Disturbance-Free 9T-ST (SSDF 9T-ST) SRAM cell, provides numerous benefits, especially in terms of achieving high stability. This paper begins by detailing the analysis of the SSDF 9T-ST cell, emphasizing its stability during read operations. The SSDF 9T-ST SRAM cell exhibits a 1.23 times improvement in read stability compared to FD 10T SRAM cells and an impressive 2.3 times improvement compared to conventional SRAM cells. Efficient write assist is crucial for achieving fast write access into stable SSDF 9T-ST SRAM cell. This work presents a High-Speed Boosted Bit-Line Swing and Collapsed Supply Write Assist Design for Stable 9T-ST SRAM. Boosting the BIT-line swing and scaling the supply are crucial strategies focused on improving the speed and efficiency of the memory write process. By amplifying the voltage swing on the BIT-line, the write operation becomes faster and more efficient. In comparison to conventional, ultra dynamic scaled supply write (UDSS), Negative-Charge Boosted BIT-line (NCBBL), and Reconfigurable Negative BIT-line Collapsed-Supply (RNBLCS) write driver circuits, proposed boosted BIT-line swing and collapsed supply (BBSCS) for 9T SRAM cell has optimized write access delays of 0.74X, 0.41X, 0.32X and 0.21X, improvement in write margin (WM) of 1.51X, 1.34X, 1.22X and 1.12X respectively. The BBSCS Write driver circuit is implemented using a custom compiler (Synopsys) through a 28&#xa0;nm BSIM4 model card for bulk CMOS. MC simulation results are monitored on Cosmoscope wave viewer (Synopsys).</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

A novel design of high-speed write assist design for single-stacked 9T-ST SRAM

  • 期刊论文

  • 发表日期：

    2025年1月14日

查看全文
  • Chokkakula Ganesh,
  • A. Sai Kumar,
  • S. K. Shoukath Vali,
  • Srinivasa Rao Karumuri,
  • Girija Sravani Kondavitee

摘要

The integration of Schmitt trigger-based (ST) SRAM cell architecture, particularly into the design of the Single-Stacked Disturbance-Free 9T-ST (SSDF 9T-ST) SRAM cell, provides numerous benefits, especially in terms of achieving high stability. This paper begins by detailing the analysis of the SSDF 9T-ST cell, emphasizing its stability during read operations. The SSDF 9T-ST SRAM cell exhibits a 1.23 times improvement in read stability compared to FD 10T SRAM cells and an impressive 2.3 times improvement compared to conventional SRAM cells. Efficient write assist is crucial for achieving fast write access into stable SSDF 9T-ST SRAM cell. This work presents a High-Speed Boosted Bit-Line Swing and Collapsed Supply Write Assist Design for Stable 9T-ST SRAM. Boosting the BIT-line swing and scaling the supply are crucial strategies focused on improving the speed and efficiency of the memory write process. By amplifying the voltage swing on the BIT-line, the write operation becomes faster and more efficient. In comparison to conventional, ultra dynamic scaled supply write (UDSS), Negative-Charge Boosted BIT-line (NCBBL), and Reconfigurable Negative BIT-line Collapsed-Supply (RNBLCS) write driver circuits, proposed boosted BIT-line swing and collapsed supply (BBSCS) for 9T SRAM cell has optimized write access delays of 0.74X, 0.41X, 0.32X and 0.21X, improvement in write margin (WM) of 1.51X, 1.34X, 1.22X and 1.12X respectively. The BBSCS Write driver circuit is implemented using a custom compiler (Synopsys) through a 28 nm BSIM4 model card for bulk CMOS. MC simulation results are monitored on Cosmoscope wave viewer (Synopsys).