Power-efficient VLSI realization of decimal convolution algorithms for resource-constrained environments: a design perspective in CMOS and double-gate CMOS technology

The field of VLSI involves designing and fabricating microchips that integrate a large number of electronic components onto a single semiconductor substrate, enabling advanced electronic systems in a compact form. Decimal convolution algorithms play a crucial role in various applications, including digital signal processing, image processing, and neural network, by efficiently processing decimal numbers. This paper proposes the VLSI implementation of decimal convolution algorithms for resource-constrained environments by leveraging parallel circuitry as well as energy-efficient. Low-power VLSI techniques like precision arithmetic operations and customized adder circuitry have also incorporated to enhance energy efficiency. The proposed design is verified through Verilog simulations and synthesized in Vivado (xc7vx485tffg1157-1) to estimate VLSI performance metrics. The simulation result of the designs exhibited 10 ns delay for a clock cycle of 5 ns along-with less than 40% resource utilization from it’s counterpart. The results offer valuable insights and potential directions for developing energy-efficient solutions for discrete number-convolution algorithms. To investigate its feasibility in future as a function of scaling in sub-micron regime, double-gate (DG) CMOS technology, the BSIM-IMG has been explored at the circuit level. The power metrics of the various components of the convolution circuitry have been compared with the CMOS counterparts.