Thickness-dependent effect of vacuum annealing on multilayer MoS2 transistors
摘要
While vacuum annealing is a widely used strategy to enhance the performance of two-dimensional electronic devices, its efficacy across the multilayer regime remains poorly understood. In this work, we present a systematic study revealing the thickness-dependent electrical and structural responses of multilayer MoS2 transistors to vacuum annealing. For statistical analysis, 36 multilayer MoS2 bottom-gate transistors were fabricated on SiO2/Si substrates with channel thicknesses ranging from 5 to 160 nm. Thin MoS2 channels with thickness below ~ 40 nm exhibited pronounced mobility enhancement and reduced hysteresis after vacuum annealing, whereas thicker flakes showed minimal improvement or degraded device performance. Raman spectroscopy correlated this contrast with the synergistic effects of surface desorption and the development of tensile stress. In thinner devices, these effect permeate the entire channel. However, in thick devices, they are effectively diluted and electrostatically screened by the bulk-like volume, confining modifications to a narrow near-surface region. These findings establish the critical role of channel thickness in governing annealing-induced modifications in multilayer MoS2 devices, providing valuable guidance for optimizing multilayer transition metal dichalcogenide transistors for reliable electronic and optoelectronic applications.