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<p>In this work, a novel integration of plasma-enhanced atomic layer deposited (PEALD) Al<sub>2</sub>O<sub>3</sub> as a high-k buffer layer with Bi₄Ti₃O₁₂ (BIT) ferroelectric films were implemented to significantly enhance the performance of ferroelectric memory devices based on Metal/Ferroelectric/Insulator/Silicon (MFeIS) and Metal/Ferroelectric/Insulator/Metal (MFeIM) architectures. The optimized MFeIS device incorporating a 10&#xa0;nm Al<sub>2</sub>O<sub>3</sub>buffer layer exhibited a maximum memory window of 7.5&#xa0;V, a substantial improvement over the 3.3&#xa0;V observed in traditional MFeS structures. The MFeIM and MFeIS devices demonstrated maximum remnant polarization values of 4.35 µC/cm² and 4.9 µC/cm², respectively. Moreover, the MFeIS devices exhibited ultra-low leakage current densities (as low as 5.41 × 10⁻⁹ A/cm²), robust endurance exceeding 10⁷ read/write cycles, and data retention projected for over 10 years. These superior performance metrics are attributed to the role of the Al<sub>2</sub>O<sub>3</sub> buffer layer in mitigating interfacial defects and suppressing charge carrier migration, thereby stabilizing the ferroelectric-semiconductor interface. The reliability of the stack was further validated through breakdown voltage analysis, which revealed a notable enhancement from 35&#xa0;V (MFeS) to 46&#xa0;V (MFeIS with 10&#xa0;nm Al<sub>2</sub>O<sub>3</sub><b>)</b>. These results underscore the strong potential of BIT/ Al<sub>2</sub>O<sub>3</sub>/Si gate stacks for high-endurance, non-volatile memory applications in next-generation ferroelectric field-effect transistor (FeFET) technologies.</p>

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Improved ferroelectric properties of mfeis devices with PEALD Al2O3 buffer for non-volatile memory applications

  • 期刊论文

  • 发表日期：

    2025年8月11日

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  • Rajesh Kumar Jha

摘要

In this work, a novel integration of plasma-enhanced atomic layer deposited (PEALD) Al2O3 as a high-k buffer layer with Bi₄Ti₃O₁₂ (BIT) ferroelectric films were implemented to significantly enhance the performance of ferroelectric memory devices based on Metal/Ferroelectric/Insulator/Silicon (MFeIS) and Metal/Ferroelectric/Insulator/Metal (MFeIM) architectures. The optimized MFeIS device incorporating a 10 nm Al2O3buffer layer exhibited a maximum memory window of 7.5 V, a substantial improvement over the 3.3 V observed in traditional MFeS structures. The MFeIM and MFeIS devices demonstrated maximum remnant polarization values of 4.35 µC/cm² and 4.9 µC/cm², respectively. Moreover, the MFeIS devices exhibited ultra-low leakage current densities (as low as 5.41 × 10⁻⁹ A/cm²), robust endurance exceeding 10⁷ read/write cycles, and data retention projected for over 10 years. These superior performance metrics are attributed to the role of the Al2O3 buffer layer in mitigating interfacial defects and suppressing charge carrier migration, thereby stabilizing the ferroelectric-semiconductor interface. The reliability of the stack was further validated through breakdown voltage analysis, which revealed a notable enhancement from 35 V (MFeS) to 46 V (MFeIS with 10 nm Al2O3). These results underscore the strong potential of BIT/ Al2O3/Si gate stacks for high-endurance, non-volatile memory applications in next-generation ferroelectric field-effect transistor (FeFET) technologies.