Modeling of the reflectance of multilayered structured semiconductor surfaces

A rigorous model in the far-field for the calculation of the broadband reflectance of multilayered structured semiconductor surfaces is introduced and is applied on semiconductor wafers with single or multiple vias or trenches. The model is based on four assumptions: (1) the wafer can be divided into units containing a single via or trench, (2) each unit can be divided into subregions, (3) the reflectance of each subregion can be simulated by the reflectance of a layer stack, and (4) the reflectance of the unit can be composed from the reflectance of each subregion, weighted with the ratio of the subregion area to the unit area, and multiplied with a phase factor that considers the depth (or height) relative to the wafer surface. As in the model the via and the wafer surface are clearly separated it is possible to study transparent coatings on the wafer surface as well as transparent fillings of the via or trench. The influence of inclined walls and a curved via bottom is investigated. Dependences upon the via depth and the ratio of via and unit area are shown and discussed.