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<p>Conventional unified power quality conditioner (UPQC) typically requires numerous power devices and exhibits excessively complex control architectures, resulting in a high computational burden. To address these limitations, this study proposes a novel UPQC topology based on an eighteen switch reused dual-output three-level converter (18S-RDO-TLC). In addition, a time-sharing coordinated finite control set model predictive control (FCS-MPC) strategy is introduced to enhance dynamic performance, while significantly reducing the computational burden associated with the predictive control process. Through comprehensive operational analysis of the proposed 18S-RDO-TLC-UPQC topology and the systematic integration of FCS-MPC with direct control principles, a predictive model in the <i>αβ</i> reference frame is established, and reference current generation algorithms based on direct control are presented for both series and shunt converters. This approach enables predictive direct control without the need to use phase-locked loops, harmonic detection, or complex coordinate transformations, thereby simplifying the control system and mitigating compensation challenges. Furthermore, the proposed strategy optimizes computational efficiency by reducing the number of optimization computations required per control cycle, further decreasing the overall computational load. Compared to a conventional three-level back-to-back UPQC under traditional FCS-MPC, the proposed topology reduces the number of power switches by 25%, and the required optimization computations per control cycle by approximately 57.81–78.91%. This strategy enables time-sharing coordinated FCS-MPC direct control of the 18S-RDO-TLC-UPQC, thereby significantly improving compensation performance. The effectiveness of the proposed topology and control strategy is validated through simulations and hardware-in-the-loop (HIL) experiments.</p>

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An improved time-sharing coordinated model predictive control for computational burden reduction in switch reused three-level converter unified power quality conditioner

  • 期刊论文

  • 发表日期：

    2025年12月6日

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  • Qigang Du,
  • Guifeng Wang,
  • Chao Luo,
  • Jinling Ji,
  • Zhifang Lin,
  • Binghua Zhang,
  • Xiangxin Fan

摘要

Conventional unified power quality conditioner (UPQC) typically requires numerous power devices and exhibits excessively complex control architectures, resulting in a high computational burden. To address these limitations, this study proposes a novel UPQC topology based on an eighteen switch reused dual-output three-level converter (18S-RDO-TLC). In addition, a time-sharing coordinated finite control set model predictive control (FCS-MPC) strategy is introduced to enhance dynamic performance, while significantly reducing the computational burden associated with the predictive control process. Through comprehensive operational analysis of the proposed 18S-RDO-TLC-UPQC topology and the systematic integration of FCS-MPC with direct control principles, a predictive model in the αβ reference frame is established, and reference current generation algorithms based on direct control are presented for both series and shunt converters. This approach enables predictive direct control without the need to use phase-locked loops, harmonic detection, or complex coordinate transformations, thereby simplifying the control system and mitigating compensation challenges. Furthermore, the proposed strategy optimizes computational efficiency by reducing the number of optimization computations required per control cycle, further decreasing the overall computational load. Compared to a conventional three-level back-to-back UPQC under traditional FCS-MPC, the proposed topology reduces the number of power switches by 25%, and the required optimization computations per control cycle by approximately 57.81–78.91%. This strategy enables time-sharing coordinated FCS-MPC direct control of the 18S-RDO-TLC-UPQC, thereby significantly improving compensation performance. The effectiveness of the proposed topology and control strategy is validated through simulations and hardware-in-the-loop (HIL) experiments.