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<p>As the core material for Integrated Circuits (ICs) manufacturing, the surface quality of silicon wafer directly affects the performance and reliability of the ICs. Chemical mechanical polishing (CMP) technology is currently considered to be the only process that can achieve overall flatness of large-size silicon wafers, and the polishing accuracy directly determines the surface quality and performance of silicon wafers. Based on the theoretical research and engineering progress of CMP technology, this review systematically explores the key scientific and technical issues in CMP. First, the synergistic mechanism of abrasive properties (such as morphology, particle size distribution, etc.) and chemical additives (such as pH regulators, oxidants, surfactants, etc.) in polishing slurry system is deeply analyzed, revealing the regulation of material removal rate (MRR) and surface roughness (Ra); Secondly, the micro-nano structure design (such as porosity, groove texture) of polishing pads and the influence factors of surface finishing technology on interface mass transfer behavior and polishing uniformity is explained; Then, the material removal mechanism model construction method based on molecular dynamics and contact mechanics is systematically summarized, and the application potential of multi-dimensional modeling in the CMP process is explored; Finally, the sources of wafer surface defects (such as particle contamination, mechanical scratches, chemical residues, etc.) after CMP and the suppression strategies are comprehensively analyzed. By integrating the innovative research results in recent years, this review reveals the structure-activity relationship of process parameters, material properties and interface behavior, and points out the challenges and development trends of CMP technology: including the development of green and environmentally friendly polishing slurry, the design of multifunctional polishing pads, in-depth research on atomic-scale removal mechanisms, and innovations in high-precision defects detection technology. This review aims to provide researchers with a systematic understanding of CMP technology, and provide theoretical references for optimizing the design of polishing slurry and polishing pads and in-depth research on polishing mechanisms, thereby promoting the further application and development of CMP technology in ultra-large-scale integrated circuit (VLSI) manufacturing and laying a solid foundation for the next generation of semiconductor devices.</p>

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Research progress in chemical mechanical polishing (CMP) of silicon wafers for integrated circuits

  • 期刊论文

  • 发表日期：

    2026年3月13日

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  • Zuozuo Wu,
  • Zhonghua Zhu,
  • Yiting Li,
  • Daming Wang,
  • Yangjian Li,
  • Shuai Yuan,
  • Jianwei Cao,
  • Deren Yang

摘要

As the core material for Integrated Circuits (ICs) manufacturing, the surface quality of silicon wafer directly affects the performance and reliability of the ICs. Chemical mechanical polishing (CMP) technology is currently considered to be the only process that can achieve overall flatness of large-size silicon wafers, and the polishing accuracy directly determines the surface quality and performance of silicon wafers. Based on the theoretical research and engineering progress of CMP technology, this review systematically explores the key scientific and technical issues in CMP. First, the synergistic mechanism of abrasive properties (such as morphology, particle size distribution, etc.) and chemical additives (such as pH regulators, oxidants, surfactants, etc.) in polishing slurry system is deeply analyzed, revealing the regulation of material removal rate (MRR) and surface roughness (Ra); Secondly, the micro-nano structure design (such as porosity, groove texture) of polishing pads and the influence factors of surface finishing technology on interface mass transfer behavior and polishing uniformity is explained; Then, the material removal mechanism model construction method based on molecular dynamics and contact mechanics is systematically summarized, and the application potential of multi-dimensional modeling in the CMP process is explored; Finally, the sources of wafer surface defects (such as particle contamination, mechanical scratches, chemical residues, etc.) after CMP and the suppression strategies are comprehensively analyzed. By integrating the innovative research results in recent years, this review reveals the structure-activity relationship of process parameters, material properties and interface behavior, and points out the challenges and development trends of CMP technology: including the development of green and environmentally friendly polishing slurry, the design of multifunctional polishing pads, in-depth research on atomic-scale removal mechanisms, and innovations in high-precision defects detection technology. This review aims to provide researchers with a systematic understanding of CMP technology, and provide theoretical references for optimizing the design of polishing slurry and polishing pads and in-depth research on polishing mechanisms, thereby promoting the further application and development of CMP technology in ultra-large-scale integrated circuit (VLSI) manufacturing and laying a solid foundation for the next generation of semiconductor devices.