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<p>High-speed, low- power comparators are an essential element of modern ADCs, especially for biomedical and mixed-signal VLSI systems. This work proposes a novel Double Tail comparator with Clock Shaped (DTCS) Controlled device. The DTCS achieves low-power, low-jitter operation due to the pre-amplification process. By using clocked-tail transistors, the pre-amplifier and latch stages are isolated, and early voltage gain is achieved by minimizing dynamic charge sharing among internal nodes. These improvements cumulatively reduce the energy dissipated per decision. It is designed in a 65&#xa0;nm CMOS process with a supply voltage of 1. 1.1&#xa0;V. The comparator can operate at speeds up to 1&#xa0;GHz and can drive a load of 10 fF. Simulations are carried out in the Cadence Virtuoso environment, and the results show a propagation delay of 120–150&#xa0;ps and a power consumption of 13–18&#xa0;µW. Also, input- referred noise of 0. 0.8&#xa0;µV RMS and a power- delay product of 2. 03 fJ are reported, which outperform conventional double- tail designs. Benchmarking against recent state- of- the- art comparators, the proposed model highlights a balanced optimization of speed, power, and noise. Compared with state-of-the-art models, the DTCS achieves a 22. 2% reduction in power consumption, and 11. 7% reduction in delay, and a 16. 11.7% reduction in leakage power. This design utility is demonstrated through an ECG acquisition as a case study. The performance is measured by Signal- to- Noise- and- Distortion Ratio (SNDR), Effective Number of Bits (ENOB), and Spurious- Free Dynamic Range (SFDR). The post- simulation results show remarkable improvements of 7% in ENOB, 12. 2% in SFDR, and 9. 9.4% in SNDR. Hence, the proposed work demonstrates a scalable, low-noise, and energy-efficient comparator that establishes a strong and reliable foundation for next-generation high-speed, low-power ADCs, particularly suited for biomedical signal processing and mixed-signal VLSI applications.</p>

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An Energy-Efficient Double-Tail Current-Shaped Comparator for High-Speed Low-Power SAR ADCs for ECG Filtering

  • 期刊论文

  • 发表日期：

    2026年7月31日

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  • Dinesh Kumar Jayaraman Rajendiran,
  • K. Priyadharsini,
  • C. Ganesh Babu,
  • S. P. Karthi

摘要

High-speed, low- power comparators are an essential element of modern ADCs, especially for biomedical and mixed-signal VLSI systems. This work proposes a novel Double Tail comparator with Clock Shaped (DTCS) Controlled device. The DTCS achieves low-power, low-jitter operation due to the pre-amplification process. By using clocked-tail transistors, the pre-amplifier and latch stages are isolated, and early voltage gain is achieved by minimizing dynamic charge sharing among internal nodes. These improvements cumulatively reduce the energy dissipated per decision. It is designed in a 65 nm CMOS process with a supply voltage of 1. 1.1 V. The comparator can operate at speeds up to 1 GHz and can drive a load of 10 fF. Simulations are carried out in the Cadence Virtuoso environment, and the results show a propagation delay of 120–150 ps and a power consumption of 13–18 µW. Also, input- referred noise of 0. 0.8 µV RMS and a power- delay product of 2. 03 fJ are reported, which outperform conventional double- tail designs. Benchmarking against recent state- of- the- art comparators, the proposed model highlights a balanced optimization of speed, power, and noise. Compared with state-of-the-art models, the DTCS achieves a 22. 2% reduction in power consumption, and 11. 7% reduction in delay, and a 16. 11.7% reduction in leakage power. This design utility is demonstrated through an ECG acquisition as a case study. The performance is measured by Signal- to- Noise- and- Distortion Ratio (SNDR), Effective Number of Bits (ENOB), and Spurious- Free Dynamic Range (SFDR). The post- simulation results show remarkable improvements of 7% in ENOB, 12. 2% in SFDR, and 9. 9.4% in SNDR. Hence, the proposed work demonstrates a scalable, low-noise, and energy-efficient comparator that establishes a strong and reliable foundation for next-generation high-speed, low-power ADCs, particularly suited for biomedical signal processing and mixed-signal VLSI applications.