Noise reduction techniques have become indispensable in various image processing applications to enhance visual quality and facilitate subsequent image processing tasks such as segmentation and classification. Noise distorts structural and other critical information in an image, thereby degrading its quality. Therefore, obtaining high-quality images is essential for accurate analysis and interpretation. In this research, an Optimized Median and Random Impulse Noise Filtering Technique (OMRINFT) with a \(3 \times 3\) window size is proposed to eliminate Random-Valued Impulse Noise (RVIN) while preserving image quality and enhancing image features. The proposed filter replaces the current processing pixel with a new pixel using a valid pixel quantification and adaptive thresholding mechanism that effectively handles random-valued impulse noise. In order to test the performance of the proposed median filter, experimental analysis was performed on six standard gray scale images of size \(512 \times 512\) (Lena, Baboon, Pepper, Cameraman, Living Room, and Bridge) and corrupted with random valued impulse noise at noise densities ranging from 10% to 90%. The entire architecture design was carried out on Xilinx Vivado 2022.1 design suite and using PYNQ-Z2 FPGA platform (XC7Z020CLG400-1). The PYNQ overlay framework was used in the Jupyter Notebook environment to perform hardware validation and real-time image processing. The experimental outcomes demonstrate that the proposed design achieves superior denoising performance compared to the existing state of the art denoising techniques. The formulated design achieves an average PSNR of 25.83 dB with an improvement of 2.32 dB ( \(\sim 9.87\%\) ) compared to the best performing existing method. Moreover, it achieves an average improvement of 3.62% in SSIM, 27.85% reduction in MSE and 13.58% in IEF, which shows that it has a better structural preservation, lower reconstruction error and has a better image restoration quality. At the hardware level, the design reduces utilization of Slice LUTs by 4.56%, Slice Registers by 3.60%, LUT-as-Memory by 5.28%, Bonded I/O by 3.53%, and BRAM by 30% as compared to the existing state-of-the-art implementations. Besides, the architecture achieves a minimum critical path delay of 1.801ns, a power dissipation of 1.459W, and a maximum throughput of 6; which is 50% higher than throughput performances of similar architectures. Additionally, the proposed median sorting architecture computes the median of nine input pixels using only 19 comparators. These improvements render the design well-suited for real-time image processing systems, where speed and the reconstruction of noisy images are essential constraints.
