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<p>With the growing demand for high-resolution (e.g., 4&#xa0;K/8&#xa0;K) and high-frame-rate video in embedded systems, traditional compression codecs struggle to balance real-time performance with compression efficiency. Field-Programmable Gate Array (FPGA)-based acceleration offers a promising solution but faces challenges in adapting neural network-based approaches to hardware constraints. This paper proposes a real-time video compression framework called DCNv2-RNN Framework on FPGA, which combines the second version of deformable convolutional networks (DCNv2) with recurrent neural networks (RNNs) for spatial–temporal encoding, optimized for FPGA deployment on a super-resolution dataset video. The framework employs INT8/fixed-point quantization and pruning to reduce computational overhead while maintaining video quality. On-board experiments demonstrate that the system achieves compression on Xilinx Zynq FPGAs, with Python also using a 49.5% lower bit-rate than H.264, while maintaining equivalent PSNR/SSIM quality, and improves compression efficiency by 26% over Improved Rate-Distortion CNN-based Auto Encoders. With hardware optimizations, it reduces BRAM use by 32% and LUT consumption by 41%, making it ideal for resource-constrained devices. In addition, it also provides sub-1&#xa0;ms latency per frame and achieves 150 Mbps throughput, which is 3.2 × faster than the spatial–temporal auto-encoders, Quality. Further, it offers a 22.7% improvement in compression efficiency over HEVC, and uses 15.8% less power so it’s well suited for real-time, power-sensitive, applications. These advances prove the DCNv2-RNN framework as better algorithm in terms of better computational efficiency and better compression performance.</p>

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Real-Time FPGA-Accelerated Video Compression Using DCNv2-RNN Framework for High-Resolution and High-Frame-Rate Applications

  • 期刊论文

  • 发表日期：

    2026年7月23日

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  • Khadir Mohammad,
  • Farukh Hashmi Mohammad

摘要

With the growing demand for high-resolution (e.g., 4 K/8 K) and high-frame-rate video in embedded systems, traditional compression codecs struggle to balance real-time performance with compression efficiency. Field-Programmable Gate Array (FPGA)-based acceleration offers a promising solution but faces challenges in adapting neural network-based approaches to hardware constraints. This paper proposes a real-time video compression framework called DCNv2-RNN Framework on FPGA, which combines the second version of deformable convolutional networks (DCNv2) with recurrent neural networks (RNNs) for spatial–temporal encoding, optimized for FPGA deployment on a super-resolution dataset video. The framework employs INT8/fixed-point quantization and pruning to reduce computational overhead while maintaining video quality. On-board experiments demonstrate that the system achieves compression on Xilinx Zynq FPGAs, with Python also using a 49.5% lower bit-rate than H.264, while maintaining equivalent PSNR/SSIM quality, and improves compression efficiency by 26% over Improved Rate-Distortion CNN-based Auto Encoders. With hardware optimizations, it reduces BRAM use by 32% and LUT consumption by 41%, making it ideal for resource-constrained devices. In addition, it also provides sub-1 ms latency per frame and achieves 150 Mbps throughput, which is 3.2 × faster than the spatial–temporal auto-encoders, Quality. Further, it offers a 22.7% improvement in compression efficiency over HEVC, and uses 15.8% less power so it’s well suited for real-time, power-sensitive, applications. These advances prove the DCNv2-RNN framework as better algorithm in terms of better computational efficiency and better compression performance.