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<p>Discrete Hartley Transform (DHT) has gained importance over the years due to its property of having real operations only, which makes its VLSI implementation sustainable, economical, and less complex. The paper presents a new algorithm which is recursive in nature and its Infinite Impulse Response (IIR) filter structure for the Discrete Hartley Transform’s computation for an input sequence of length N, where <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\( N = 2^m \)</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mi>N</mi> <mo>=</mo> <msup> <mn>2</mn> <mi>m</mi> </msup> </mrow> </math></EquationSource> </InlineEquation> and <InlineEquation ID="IEq2"> <EquationSource Format="TEX">\( m \ge 4 \)</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mi>m</mi> <mo>≥</mo> <mn>4</mn> </mrow> </math></EquationSource> </InlineEquation>. The VLSI implementation of the IIR filter structure was carried out using Verilog design on Xilinx Vivado 2023.1 for Artix-7 (xc7a100tcsg3241). The proposed IIR structure was also validated by simulating it in MATLAB Simulink, and the functionality of the VLSI implementation was verified. The proposed folding recursive algorithm can compute the DHT with minimum hardware complexity, which is highly useful in real-life applications.</p>

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Novel Algorithm for the Discrete Hartley Transform and its Recursive Structure with VLSI Implementation

  • 期刊论文

  • 发表日期：

    2026年7月8日

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  • Dhwani Kaushal,
  • Vivek Singh,
  • Priyanka Jain

摘要

Discrete Hartley Transform (DHT) has gained importance over the years due to its property of having real operations only, which makes its VLSI implementation sustainable, economical, and less complex. The paper presents a new algorithm which is recursive in nature and its Infinite Impulse Response (IIR) filter structure for the Discrete Hartley Transform’s computation for an input sequence of length N, where \( N = 2^m \) N = 2 m and \( m \ge 4 \) m ≥ 4 . The VLSI implementation of the IIR filter structure was carried out using Verilog design on Xilinx Vivado 2023.1 for Artix-7 (xc7a100tcsg3241). The proposed IIR structure was also validated by simulating it in MATLAB Simulink, and the functionality of the VLSI implementation was verified. The proposed folding recursive algorithm can compute the DHT with minimum hardware complexity, which is highly useful in real-life applications.