<p>Video Super-Resolution (VSR) is an open video technology commonly deployed in high-definition devices, including HDTVs and smartphones, and requires the generation of high-resolution frames from the low-resolution frames into full HD. Hardware implementation of CNN-based VSR is challenging since traditional multipliers and repeated constant multiplications consume more power, space, and time. To overcome these issues, this paper proposes a Hamming Boolean Merging (HBM) based Approximate Multiple Constant Multiplication (AMCM) architecture in a CNN accelerator, which is optimized through Compatible Graph Synthesis (CGS). In the proposed approach, similar binary patterns are identified using Hamming distance and merged to eliminate redundant shift and add operations to reduce the number of active components. The CGS technique is used to enhance the performance by reusing compatible arithmetic nodes, which leads to compact hardware design and lower power usage. Experimental results are simulated in the Xilinx ZCU106 FPGA platform indicate that the proposed HBM-AMCM requires 51.5% of the total gate count and 69% of the gates used in the hard-coded implementation. The proposed method also demonstrates a high VSR quality of PSNR 45.02&#xa0;dB, SSIM 0.987 and RRMSE of 2.01which is better than other MCM designs. Overall, the power consumption of the proposed method is 27.247%, 55.190%, 45.588% and 30.563% lower than the existing methods, Mint, MEP V-CNN, DVS-based HR, and TACBM, respectively.</p>