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<p>In many applications, such as image processing and neural networks, maximum and minimum value detection circuits are widely used. However, until now, no circuit has been capable of simultaneously providing both the maximum and minimum input voltages at the output. In this paper, a low-power solution is presented for applications that require both the winning and losing input signals at the same time. A novel simultaneous Winner-Take-All (WTA) and Loser-Take-All (LTA) circuit is introduced, which reduces power consumption by approximately 60% compared to conventional structures, where the WTA and LTA circuits are implemented separately, through the use of a current sharing technique. The proposed circuit has been designed and simulated using 0.18&#xa0;µm CMOS technology. The power consumption of the proposed circuit is 2.359&#xa0;µW. It demonstrates over 96% accuracy for 5&#xa0;MHz input signals within a 1&#xa0;V dynamic range. The proposed circuit has also been employed in an image processing algorithm for edge detection, resulting in significant power savings.</p>

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A Power-Efficient Analog Circuit for Winner-Take-All and Loser-Take-All Implementation for Edge Detection Applications

  • 期刊论文

  • 发表日期：

    2026年5月4日

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  • HosseinYaghoobzadeh Shadmehri,
  • Mohammad Tavakkoli Ghouchani,
  • Gholamreza Jafari,
  • Ehsan Rahiminejad

摘要

In many applications, such as image processing and neural networks, maximum and minimum value detection circuits are widely used. However, until now, no circuit has been capable of simultaneously providing both the maximum and minimum input voltages at the output. In this paper, a low-power solution is presented for applications that require both the winning and losing input signals at the same time. A novel simultaneous Winner-Take-All (WTA) and Loser-Take-All (LTA) circuit is introduced, which reduces power consumption by approximately 60% compared to conventional structures, where the WTA and LTA circuits are implemented separately, through the use of a current sharing technique. The proposed circuit has been designed and simulated using 0.18 µm CMOS technology. The power consumption of the proposed circuit is 2.359 µW. It demonstrates over 96% accuracy for 5 MHz input signals within a 1 V dynamic range. The proposed circuit has also been employed in an image processing algorithm for edge detection, resulting in significant power savings.