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<p>Hazy weather conditions significantly compromise the reliability of real-time vision systems, such as ADAS and surveillance. While existing dehazing methods can achieve high visual quality, they often rely on computationally intensive patch-based processing, leading to increased latency and hardware overhead. This work presents a hardware-efficient, saturation-based image dehazing framework tailored for real-time VLSI implementation. The proposed architecture incorporates an intelligent pre-processing stage using a lightweight CNN classifier to selectively bypass the dehazing pipeline for clear frames, thereby improving system-level power efficiency. To mitigate halo artifacts without incurring the cost of conventional refinement filters, a pixel-level, saturation-based transmission map estimation is employed. The framework is evaluated on both synthetic and real-world hazy datasets, including RESIDE and O-HAZE, encompassing multiple haze densities and illumination conditions. An extensive ablation study is conducted to analyze the impact of filter size, saturation control parameter (ψ), and haze severity on restoration performance and hardware complexity. Comparative evaluation against state-of-the-art patch-based and DCP-based baselines demonstrates consistent performance gains, achieving a peak Structural Similarity Index (SSIM) of 0.970 across varying haze conditions. Hardware synthesis on FPGA and ASIC platforms further confirms that the proposed methodological shift enables higher operating frequency and lower power consumption. The ASIC implementation achieves up to 36.12% area reduction, 57.47% delay improvement, and 69.99% power savings, demonstrating the design’s suitability for high-performance ADAS applications under diverse environmental conditions.</p>

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Real-Time Saturation-Driven Image Dehazing: An FPGA and ASIC Design Approach

  • 期刊论文

  • 发表日期：

    2026年4月1日

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  • Harish Babu Gade,
  • Venkata Krishna Odugu,
  • Nikhil Srinivas Charugundla,
  • Abhishek Inguva,
  • Chinthareddy Viswathez Reddy,
  • Banothu Bapuji

摘要

Hazy weather conditions significantly compromise the reliability of real-time vision systems, such as ADAS and surveillance. While existing dehazing methods can achieve high visual quality, they often rely on computationally intensive patch-based processing, leading to increased latency and hardware overhead. This work presents a hardware-efficient, saturation-based image dehazing framework tailored for real-time VLSI implementation. The proposed architecture incorporates an intelligent pre-processing stage using a lightweight CNN classifier to selectively bypass the dehazing pipeline for clear frames, thereby improving system-level power efficiency. To mitigate halo artifacts without incurring the cost of conventional refinement filters, a pixel-level, saturation-based transmission map estimation is employed. The framework is evaluated on both synthetic and real-world hazy datasets, including RESIDE and O-HAZE, encompassing multiple haze densities and illumination conditions. An extensive ablation study is conducted to analyze the impact of filter size, saturation control parameter (ψ), and haze severity on restoration performance and hardware complexity. Comparative evaluation against state-of-the-art patch-based and DCP-based baselines demonstrates consistent performance gains, achieving a peak Structural Similarity Index (SSIM) of 0.970 across varying haze conditions. Hardware synthesis on FPGA and ASIC platforms further confirms that the proposed methodological shift enables higher operating frequency and lower power consumption. The ASIC implementation achieves up to 36.12% area reduction, 57.47% delay improvement, and 69.99% power savings, demonstrating the design’s suitability for high-performance ADAS applications under diverse environmental conditions.