Scholarlink

<p>This paper presents a pull–push, capacitor-less low dropout (CL-LDO) regulator with triple control loops (TCL) targeting digital logic circuits within System-on-Chip (SoC) applications. The design incorporates a dynamic super source follower (DSSF) based on the flipped voltage follower (FVF) structure and a source cross-connected error amplifier (SCC-EA) to enhance transient response. Post-layout simulations using 180-nm CMOS technology confirm stability with a 50&#xa0;pF capacitive load, utilizing only 1&#xa0;pF single Miller compensation capacitance, leading to a compact layout area of 0.021&#xa0;mm<sup>2</sup>. Operating at a 1.5&#xa0;V supply voltage, the LDO exhibits a quiescent current of 47&#xa0;μA under light load and supports up to 50&#xa0;mA load current. During rapid load transients within 100&#xa0;ns, undershoot/overshoot voltages are below 192.6&#xa0;mV/144.4&#xa0;mV, with settling times under 0.18&#xa0;μs/0.39&#xa0;μs, demonstrating robust dynamic performance, making it well-suited for integrated power management of the aforementioned load circuits in SoC systems.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

A Fast Transient Response and Area-Efficient Capacitor-Less LDO with Multiple Control Loops

  • 期刊论文

  • 发表日期：

    2026年3月6日

查看全文
  • Hang Shu,
  • Pengfei Liao,
  • Wensuo Chen

摘要

This paper presents a pull–push, capacitor-less low dropout (CL-LDO) regulator with triple control loops (TCL) targeting digital logic circuits within System-on-Chip (SoC) applications. The design incorporates a dynamic super source follower (DSSF) based on the flipped voltage follower (FVF) structure and a source cross-connected error amplifier (SCC-EA) to enhance transient response. Post-layout simulations using 180-nm CMOS technology confirm stability with a 50 pF capacitive load, utilizing only 1 pF single Miller compensation capacitance, leading to a compact layout area of 0.021 mm2. Operating at a 1.5 V supply voltage, the LDO exhibits a quiescent current of 47 μA under light load and supports up to 50 mA load current. During rapid load transients within 100 ns, undershoot/overshoot voltages are below 192.6 mV/144.4 mV, with settling times under 0.18 μs/0.39 μs, demonstrating robust dynamic performance, making it well-suited for integrated power management of the aforementioned load circuits in SoC systems.