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<p>With the rapid growth of data processing demands, the increasing data density has brought multivalued logic circuits–especially ternary logic–into the spotlight. As a fundamental unit of digital systems, the adder directly affects computation speed and serves as a key building block for many complex circuits. Compared with binary full adders, ternary adders offer significant advantages in computational efficiency, making them increasingly valuable for research. Carbon nanotube field-effect transistors (CNTFETs), with tunable threshold voltages and superior device characteristics, are well suited for ternary logic design. In this work, a novel ternary half adder is designed based on a newly proposed CNTFET unary operation circuit. Furthermore, two unbalanced ternary full adders supporting three-valued carry inputs and outputs are introduced by exploiting transistor transmission properties and embedding ternary logic algorithms. Hspice simulations at 0.5 GHz demonstrate that the proposed half adder reduces power-delay product (PDP) by 4.55%-74.18% compared with existing designs. The two proposed full adders exhibit PDP reductions of 6.99%-81.07% and 31.35%-86.02%, respectively. In addition, across various frequencies, temperatures, supply voltages, and load conditions, the proposed circuits consistently demonstrate superior performance compared with existing counterparts. Moreover, the proposed full adders attain energy efficiency comparable to, or even surpassing, the current best designs that only support two-valued carry inputs and outputs, thereby realizing higher energy efficiency while maintaining full ternary functionality.</p>

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Design of Area-Efficient and Low-Power Fully Functional Ternary Adders in CNTFET Technology

  • 期刊论文

  • 发表日期：

    2026年3月7日

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  • Binyu He,
  • Gaoyang Fan,
  • Nan Jiang,
  • Yanyun Dai

摘要

With the rapid growth of data processing demands, the increasing data density has brought multivalued logic circuits–especially ternary logic–into the spotlight. As a fundamental unit of digital systems, the adder directly affects computation speed and serves as a key building block for many complex circuits. Compared with binary full adders, ternary adders offer significant advantages in computational efficiency, making them increasingly valuable for research. Carbon nanotube field-effect transistors (CNTFETs), with tunable threshold voltages and superior device characteristics, are well suited for ternary logic design. In this work, a novel ternary half adder is designed based on a newly proposed CNTFET unary operation circuit. Furthermore, two unbalanced ternary full adders supporting three-valued carry inputs and outputs are introduced by exploiting transistor transmission properties and embedding ternary logic algorithms. Hspice simulations at 0.5 GHz demonstrate that the proposed half adder reduces power-delay product (PDP) by 4.55%-74.18% compared with existing designs. The two proposed full adders exhibit PDP reductions of 6.99%-81.07% and 31.35%-86.02%, respectively. In addition, across various frequencies, temperatures, supply voltages, and load conditions, the proposed circuits consistently demonstrate superior performance compared with existing counterparts. Moreover, the proposed full adders attain energy efficiency comparable to, or even surpassing, the current best designs that only support two-valued carry inputs and outputs, thereby realizing higher energy efficiency while maintaining full ternary functionality.