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<p>Comparators play a vital role in digital and mixed-signal systems, enabling fast and accurate magnitude comparisons required in applications such as analog-to-digital converters (ADCs), signal processors, and arithmetic logic units. However, aggressive technology scaling, comparator circuits face critical challenges, including increased glitch activity, output voltage degradation, and heightened noise susceptibility, particularly evident during waveform simulation in nanometer-scale CMOS processes. These issues impact the reliability, speed, and power efficiency of the circuits. To address these problems, this work proposes an enhanced design methodology based on Pass Transistor Logic (PTL), incorporating load capacitors to mitigate glitches and stabilize output behavior. The work presents design and simulation of 4-bit and 8-bit PTL-based comparators in both 45 and 90&#xa0;nm CMOS technologies using Cadence Virtuoso. A comprehensive performance analysis demonstrates the effectiveness of our approach.&#xa0;Key results shows that the proposed 45&#xa0;nm 8-bit comparator achieves a power consumption of 88.26&#xa0;µW and a propagation delay of 851.8&#xa0;ps, resulting in an excellent Power-Delay Product (PDP) of 75.18 fJ. The outcome of the work represents a significant improvement over conventional designs, with the 45&#xa0;nm implementation reducing power by over 65% and PDP by over 80% compared to its 90&#xa0;nm counterpart.&#xa0;The analysis also confirms a notable reduction in output noise kickback and improved signal integrity. A comparative assessment with existing works confirms the superiority of the proposed PTL architecture in balancing reduction in area, ultra-low power, and noise immunity, making it highly suitable for advanced VLSI applications such as ADCs and arithmetic logic units.</p>

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Performance Enhanced CMOS Pass Transistor Logic Based Multi-Bit Comparators at 45 nm & 90 nm Technologies

  • 期刊论文

  • 发表日期：

    2026年3月7日

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  • H. B. Bore Gowda,
  • S. B. Rudraswamy,
  • H. R. Shashidhara

摘要

Comparators play a vital role in digital and mixed-signal systems, enabling fast and accurate magnitude comparisons required in applications such as analog-to-digital converters (ADCs), signal processors, and arithmetic logic units. However, aggressive technology scaling, comparator circuits face critical challenges, including increased glitch activity, output voltage degradation, and heightened noise susceptibility, particularly evident during waveform simulation in nanometer-scale CMOS processes. These issues impact the reliability, speed, and power efficiency of the circuits. To address these problems, this work proposes an enhanced design methodology based on Pass Transistor Logic (PTL), incorporating load capacitors to mitigate glitches and stabilize output behavior. The work presents design and simulation of 4-bit and 8-bit PTL-based comparators in both 45 and 90 nm CMOS technologies using Cadence Virtuoso. A comprehensive performance analysis demonstrates the effectiveness of our approach. Key results shows that the proposed 45 nm 8-bit comparator achieves a power consumption of 88.26 µW and a propagation delay of 851.8 ps, resulting in an excellent Power-Delay Product (PDP) of 75.18 fJ. The outcome of the work represents a significant improvement over conventional designs, with the 45 nm implementation reducing power by over 65% and PDP by over 80% compared to its 90 nm counterpart. The analysis also confirms a notable reduction in output noise kickback and improved signal integrity. A comparative assessment with existing works confirms the superiority of the proposed PTL architecture in balancing reduction in area, ultra-low power, and noise immunity, making it highly suitable for advanced VLSI applications such as ADCs and arithmetic logic units.