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<p>Effective and low-power data processing is important in modern Convolutional Neural Network (CNN) accelerators, where the key computational activity is multiple operations. Approximate computing presents an option by effectively reduces hardware complexity while maintaining sufficient accuracy. This study proposes two novel Recursive Leading One-bit-Based Approximate (RLOBA) multiplier architectures that significantly improve both the performance and accuracy metrics. The proposed design incorporates an Exact Multiplier (EM) to compute higher-order n/2-bit products, identify the Leading One-Bit (LOB) positions of both n/2-bit n segments, and produce the result through relatively simple addition, subtraction, and shift operations. All proposed and existing Approximate Multipliers (AMs) are implemented using Verilog HDL for 8–32 bit operand sizes, simulated in Vivado and MATLAB, and synthesized with the Cadence RTL Compiler. From the simulation results, the average improvements for the proposed RLOBA multiplier designs demonstrate significant reductions in delays, area, power, PDP, and EDP by 59.3%, 29.0%, 57.2%, 68.1%, and 74.8%, respectively. Furthermore, the proposed multipliers exhibit better PSNR, SSIM, and classification accuracy when integrated into Image Smoothing Filters (ISF) and several CNN models, as a demonstration of their use in high-performance, low-power approximate computing applications.</p>

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Efficient Design of Approximate Multipliers using Leading One-Bit and Recursive Approaches for Fault Tolerance in CNN Accelerators

  • 期刊论文

  • 发表日期：

    2026年2月20日

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  • E. Jagadeeswara Rao,
  • Akurathi Gangadhar,
  • Mamidipaka Hema,
  • K. V. Ramana Rao,
  • Jahed Khan

摘要

Effective and low-power data processing is important in modern Convolutional Neural Network (CNN) accelerators, where the key computational activity is multiple operations. Approximate computing presents an option by effectively reduces hardware complexity while maintaining sufficient accuracy. This study proposes two novel Recursive Leading One-bit-Based Approximate (RLOBA) multiplier architectures that significantly improve both the performance and accuracy metrics. The proposed design incorporates an Exact Multiplier (EM) to compute higher-order n/2-bit products, identify the Leading One-Bit (LOB) positions of both n/2-bit n segments, and produce the result through relatively simple addition, subtraction, and shift operations. All proposed and existing Approximate Multipliers (AMs) are implemented using Verilog HDL for 8–32 bit operand sizes, simulated in Vivado and MATLAB, and synthesized with the Cadence RTL Compiler. From the simulation results, the average improvements for the proposed RLOBA multiplier designs demonstrate significant reductions in delays, area, power, PDP, and EDP by 59.3%, 29.0%, 57.2%, 68.1%, and 74.8%, respectively. Furthermore, the proposed multipliers exhibit better PSNR, SSIM, and classification accuracy when integrated into Image Smoothing Filters (ISF) and several CNN models, as a demonstration of their use in high-performance, low-power approximate computing applications.