Scholarlink

<p>This work presents an ultra-low-power keyword spotting (KWS) processor based on algorithm-hardware co-design. First, a joint Mel frequency cepstral coefficient (MFCC) and convolutional neural network (CNN) optimization framework is proposed, where the MFCC front-end is made trainable together with the CNN classifier, enabling end-to-end co-optimization and improving robustness. Second, an energy-efficient MFCC implementation is realized by introducing ternary quantized fast Fourier Transform (FFT) and approximate multipliers, which significantly reduce arithmetic complexity while preserving classification performance. Finally, a 4-bit power-of-two (POT) quantization scheme is adopted, and a multiplier-free processing element (PE) architecture tailored to this quantization is developed, significantly reducing hardware cost. Implemented in 65-nm CMOS technology, the processor achieves 93.47% accuracy on the Google Speech Commands Dataset (GSCD), with an ultra-low power consumption of 19.28 <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(\mu\)</EquationSource> </InlineEquation>W and a core area of only 0.45 mm<InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(^2\)</EquationSource> </InlineEquation>, demonstrating superior energy efficiency and hardware compactness compared to prior designs.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

An Ultra-Low-Power Keyword-Spotting Processor with Trainable MFCC-CNN Framework and Multiplication-Efficient Acceleration

  • 期刊论文

  • 发表日期：

    2026年1月28日

查看全文
  • Zuo Zhang,
  • Yunqi Guan,
  • Wenbin Ye

摘要

This work presents an ultra-low-power keyword spotting (KWS) processor based on algorithm-hardware co-design. First, a joint Mel frequency cepstral coefficient (MFCC) and convolutional neural network (CNN) optimization framework is proposed, where the MFCC front-end is made trainable together with the CNN classifier, enabling end-to-end co-optimization and improving robustness. Second, an energy-efficient MFCC implementation is realized by introducing ternary quantized fast Fourier Transform (FFT) and approximate multipliers, which significantly reduce arithmetic complexity while preserving classification performance. Finally, a 4-bit power-of-two (POT) quantization scheme is adopted, and a multiplier-free processing element (PE) architecture tailored to this quantization is developed, significantly reducing hardware cost. Implemented in 65-nm CMOS technology, the processor achieves 93.47% accuracy on the Google Speech Commands Dataset (GSCD), with an ultra-low power consumption of 19.28 \(\mu\) W and a core area of only 0.45 mm \(^2\) , demonstrating superior energy efficiency and hardware compactness compared to prior designs.