<p>This paper proposes a fast transient flipped voltage follower (FVF) based capacitor-less low-dropout regulator with high-gain error amplifier (EA), enhanced bulk-driven feed-forward (EBDFF) technique, and active capacitor-coupled transient enhancement circuit (ACCTEC). The precision loop utilized a high-gain EA with cross-coupled (CC) and negative resistance (NR) technique to improve DC loop gain and ensure excellent DC regulation. The fast loop composed of a FVF and a non-inverting gain stage (NIGS) exhibits ultra-high bandwidth and high loop gain. The introduced EBDFF technique can effectively improve the power supply rejection (PSR) performance. The proposed ACCTEC further optimizes voltage spikes and recovery times during sudden load transitions. The proposed FVF-LDO is implemented using a 180 nm BCD process and delivers a maximum load current of 100 mA. The simulation results indicate that the output voltage is 1 V when the input voltage ranges from 1.2 V to 1.8 V. The overshoot and undershoot voltages of the LDO are 90 mV and 70 mV respectively, with recovery times both less than 500ns. PSR of the FVF-LDO is over 80 dB at 10 kHz. The FVF-LDO demonstrates a load regulation of 0.0914 μV/mA and a line regulation of 1.093 mV/V, yielding a FOM<sub>1</sub> of 54.3fs and a FOM<sub>2</sub> of 0.029 ps.</p>

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A Fast Transient FVF-LDO with Enhanced Bulk-Driven Feed-Forward Technique for Self-Powered WSNs Applications

  • Siwan Dong,
  • Dewang Wei,
  • Yangtao Hu

摘要

This paper proposes a fast transient flipped voltage follower (FVF) based capacitor-less low-dropout regulator with high-gain error amplifier (EA), enhanced bulk-driven feed-forward (EBDFF) technique, and active capacitor-coupled transient enhancement circuit (ACCTEC). The precision loop utilized a high-gain EA with cross-coupled (CC) and negative resistance (NR) technique to improve DC loop gain and ensure excellent DC regulation. The fast loop composed of a FVF and a non-inverting gain stage (NIGS) exhibits ultra-high bandwidth and high loop gain. The introduced EBDFF technique can effectively improve the power supply rejection (PSR) performance. The proposed ACCTEC further optimizes voltage spikes and recovery times during sudden load transitions. The proposed FVF-LDO is implemented using a 180 nm BCD process and delivers a maximum load current of 100 mA. The simulation results indicate that the output voltage is 1 V when the input voltage ranges from 1.2 V to 1.8 V. The overshoot and undershoot voltages of the LDO are 90 mV and 70 mV respectively, with recovery times both less than 500ns. PSR of the FVF-LDO is over 80 dB at 10 kHz. The FVF-LDO demonstrates a load regulation of 0.0914 μV/mA and a line regulation of 1.093 mV/V, yielding a FOM1 of 54.3fs and a FOM2 of 0.029 ps.