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<p>As CMOS image sensors evolve toward higher pixel density and wider dynamic range, the precision and robustness of analog front-end circuits—particularly operational amplifiers—are becoming increasingly critical. Traditional input offset calibration techniques, including physical trimming and digital correction, suffer from high area overhead, limited scalability, and poor adaptability, making them unsuitable for large-scale sensor array integration. This work presents a compact, non-volatile offset calibration scheme based on tunable memristive resistors embedded within the differential input network. Post-layout simulations in a 180&#xa0;nm CMOS process demonstrate sub-millivolt calibration accuracy for both single-device and composite mismatch conditions, achieving over 97.8% reduction in offset voltage. Key analog metrics, including gain and phase margin, are restored within 4.8% of nominal values. The proposed architecture incurs only 10.5% area overhead and eliminates the need for external references or feedback loops, offering a scalable, low-power solution for precision analog calibration in high-density sensor SoCs.</p>

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A Memristor-Based Offset Calibration for Operational Amplifiers

  • 期刊论文

  • 发表日期：

    2026年2月4日

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  • Sunfu Wei,
  • Liang Shi,
  • Hechang Lu,
  • Dengyun Lei,
  • Feng Zhang,
  • Yuan Liu

摘要

As CMOS image sensors evolve toward higher pixel density and wider dynamic range, the precision and robustness of analog front-end circuits—particularly operational amplifiers—are becoming increasingly critical. Traditional input offset calibration techniques, including physical trimming and digital correction, suffer from high area overhead, limited scalability, and poor adaptability, making them unsuitable for large-scale sensor array integration. This work presents a compact, non-volatile offset calibration scheme based on tunable memristive resistors embedded within the differential input network. Post-layout simulations in a 180 nm CMOS process demonstrate sub-millivolt calibration accuracy for both single-device and composite mismatch conditions, achieving over 97.8% reduction in offset voltage. Key analog metrics, including gain and phase margin, are restored within 4.8% of nominal values. The proposed architecture incurs only 10.5% area overhead and eliminates the need for external references or feedback loops, offering a scalable, low-power solution for precision analog calibration in high-density sensor SoCs.