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<p>This work aims to propose an area and power efficient pulse shrinking time-to-digital converter (TDC) for use in temperature sensor. The time difference between a digitally controlled delay cell (DCDC) output and a fixed reference input is compared in generating a pulse whose on-time shrunk depending upon the choice of DCDC select lines. Eventually, the pulse is fed to a gated ring oscillator to note the time difference and then an asynchronous counter to record the generation of digital code. Simulation results in a 90-nm CMOS and 1.1&#xa0;V power supply Vdd indicate a power consumption 409&#xa0;μW while attaining a competitive resolution of 25&#xa0;ps. Besides, linearity is confirmed by achieving a DNL value of 1.03 (LSB) and INL of 1.38 at 1.1&#xa0;V Vdd. Additionally, Monte Carlo study indicates a standard deviation within 0.5% to suggest robustness of the design.</p>

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A Digitally Controlled Delay Cell Based Pulse Shrinking Time-to-Digital Converter

  • 期刊论文

  • 发表日期：

    2025年10月25日

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  • Bipasha Debbarma,
  • Abir J. Mondal,
  • Sandip Bhattacharya

摘要

This work aims to propose an area and power efficient pulse shrinking time-to-digital converter (TDC) for use in temperature sensor. The time difference between a digitally controlled delay cell (DCDC) output and a fixed reference input is compared in generating a pulse whose on-time shrunk depending upon the choice of DCDC select lines. Eventually, the pulse is fed to a gated ring oscillator to note the time difference and then an asynchronous counter to record the generation of digital code. Simulation results in a 90-nm CMOS and 1.1 V power supply Vdd indicate a power consumption 409 μW while attaining a competitive resolution of 25 ps. Besides, linearity is confirmed by achieving a DNL value of 1.03 (LSB) and INL of 1.38 at 1.1 V Vdd. Additionally, Monte Carlo study indicates a standard deviation within 0.5% to suggest robustness of the design.