Scholarlink

<p>This paper presents the design and implementation of a 7th-order Leapfrog analog-to-digital converter (ADC). Each integrator of the 7th-order continuous-time (CT) filter is stabilized by local digital feedback with a single-bit quantizer, making the entire ADC as stable as a first-order continuous-time sigma-delta modulator (CT-<InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(\Sigma \Delta\)</EquationSource> </InlineEquation>M).&#xa0;Without sacrificing stability, the high filter order enables a low oversampling ratio (OSR) and provides excellent anti-alias filtering. The modular structure and low design complexity of the Leapfrog ADC make it particularly suitable for programmatic design methodologies. We demonstrate this through a custom Python-based layout compilation tool that generates the entire ADC layout from source code. Implemented in 130 nm CMOS, the prototype achieves 82 dB dynamic range and consumes 2.5 mW from a 1.5 V supply. The measured alias rejection exceeds 88 dB for signals in the 21–23 MHz band around the 22 MHz sampling frequency.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

A Compiled 7th-order Leapfrog ADC in 130 nm CMOS

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2025年10月18日

查看全文
  • Fredrik Feyling,
  • Hampus Malmberg,
  • Carsten Wulff,
  • Trond Ytterdal

摘要

This paper presents the design and implementation of a 7th-order Leapfrog analog-to-digital converter (ADC). Each integrator of the 7th-order continuous-time (CT) filter is stabilized by local digital feedback with a single-bit quantizer, making the entire ADC as stable as a first-order continuous-time sigma-delta modulator (CT- \(\Sigma \Delta\) M). Without sacrificing stability, the high filter order enables a low oversampling ratio (OSR) and provides excellent anti-alias filtering. The modular structure and low design complexity of the Leapfrog ADC make it particularly suitable for programmatic design methodologies. We demonstrate this through a custom Python-based layout compilation tool that generates the entire ADC layout from source code. Implemented in 130 nm CMOS, the prototype achieves 82 dB dynamic range and consumes 2.5 mW from a 1.5 V supply. The measured alias rejection exceeds 88 dB for signals in the 21–23 MHz band around the 22 MHz sampling frequency.