Scholarlink

<p>For system-on-a-chip designers, reducing the power consumption and ensuring high speed of IoT devices and AI applications is a top priority. This paper presents a positive edge-triggered true single-phase clock (PET-TSPC) D flip-flop (DFF) implemented using a 7-nm FinFET-based process, optimized for a wide range of supply voltages and operating temperatures. A comparative analysis with conventional 22-nm CMOS technology and 7-nm FinFET reveals the occurrence of the temperature inversion effect (TIE), a critical phenomenon at advanced nodes. Simulation results show that the proposed PET-TSPC-FF achieves a 59.2% reduction in power consumption and a 17.6% reduction in delay at 0.7&#xa0;V, compared to state-of-the-art FFs. Additionally, it achieves the lowest power-delay product (PDP) of 0.38 fJ at 0.7&#xa0;V. For a constant V<sub>DD</sub> of 0.8&#xa0;V, DFF adopting 22-nm CMOS, power consumption increases from 3.57&#xa0;μW to 4.03&#xa0;μW as temperature drops from 107° to 27&#xa0;°C, whereas DFF adopting 7-nm FinFET, it decreases from 3.1&#xa0;μW to 1.6&#xa0;μW. These results highlight how well the designed flip-flop performs in terms of energy efficiency and thermal robustness for next-generation AI and IoT hardware platforms.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Thermal Reliability Analysis for 7-nm FinFET Based Positive Edge Triggered TSPC Flip-Flop for Future IoT and AI Applications

  • 期刊论文

  • 发表日期：

    2025年10月14日

查看全文
  • Syeda Hurmath Juveria,
  • J. Ajayan,
  • R. Shashank

摘要

For system-on-a-chip designers, reducing the power consumption and ensuring high speed of IoT devices and AI applications is a top priority. This paper presents a positive edge-triggered true single-phase clock (PET-TSPC) D flip-flop (DFF) implemented using a 7-nm FinFET-based process, optimized for a wide range of supply voltages and operating temperatures. A comparative analysis with conventional 22-nm CMOS technology and 7-nm FinFET reveals the occurrence of the temperature inversion effect (TIE), a critical phenomenon at advanced nodes. Simulation results show that the proposed PET-TSPC-FF achieves a 59.2% reduction in power consumption and a 17.6% reduction in delay at 0.7 V, compared to state-of-the-art FFs. Additionally, it achieves the lowest power-delay product (PDP) of 0.38 fJ at 0.7 V. For a constant VDD of 0.8 V, DFF adopting 22-nm CMOS, power consumption increases from 3.57 μW to 4.03 μW as temperature drops from 107° to 27 °C, whereas DFF adopting 7-nm FinFET, it decreases from 3.1 μW to 1.6 μW. These results highlight how well the designed flip-flop performs in terms of energy efficiency and thermal robustness for next-generation AI and IoT hardware platforms.