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<p>Approximate computing is an emerging method for minimal energy consumption and reduced hardware complexity while improving system performance in error-tolerant applications. This research proposes two approximate multipliers: one based on approximate condition-based majority logic (ACMLC) and compensator approximate compressor (CAC), and the second based on Dadda approximate multipliers. The findings are evaluated in comparison to those of the conventional high-performance Wallace tree multiplier (WTM). The proposed multipliers are designed in Verilog HDL and evaluated through simulation on the Xilinx Vivado 2018.3 software, with the Artix-7 FPGA AC701, clocked at 200&#xa0;MHz, serving as the target platform. The proposed ACMLC and CAC-based multiplier consumes less power (6.421 W), has the shortest delay (6.62&#xa0;ns), and uses the smallest area (31 Look-up Tables (LUTs)) compared to the Dadda approximate multiplier. In addition, the ACMLC and CAC-based multiplier saves 66.30% area, 67.92% power-delay-product (PDP), 76.03% area-delay-product (ADP), and 84.8% power-area-product (PAP) as compared to the conventional Wallace multiplier. The ACMLC and CAC-based multiplier also achieves an ER of ‘1’, but with a higher MRED of <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(64.9\times {10}^{-3}\)</EquationSource> </InlineEquation> and NMED of <InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(24.25\times {10}^{-3}\)</EquationSource> </InlineEquation>, reflecting moderate approximation accuracy of 93.51%. This makes it highly energy-efficient and well-suited for Error-Resilient applications, such as image smoothing, sharpening, fusion, and blending, which are used to produce high-quality visual images.</p>

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Energy-Efficient 8-Bit Approximate Multipliers Design and Analysis for Error-Resilient Applications

  • 期刊论文

  • 发表日期：

    2025年10月5日

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  • Venkata Sudhakar Chowdam,
  • M. Venkata Naresh,
  • Ganjikunta Ganesh Kumar

摘要

Approximate computing is an emerging method for minimal energy consumption and reduced hardware complexity while improving system performance in error-tolerant applications. This research proposes two approximate multipliers: one based on approximate condition-based majority logic (ACMLC) and compensator approximate compressor (CAC), and the second based on Dadda approximate multipliers. The findings are evaluated in comparison to those of the conventional high-performance Wallace tree multiplier (WTM). The proposed multipliers are designed in Verilog HDL and evaluated through simulation on the Xilinx Vivado 2018.3 software, with the Artix-7 FPGA AC701, clocked at 200 MHz, serving as the target platform. The proposed ACMLC and CAC-based multiplier consumes less power (6.421 W), has the shortest delay (6.62 ns), and uses the smallest area (31 Look-up Tables (LUTs)) compared to the Dadda approximate multiplier. In addition, the ACMLC and CAC-based multiplier saves 66.30% area, 67.92% power-delay-product (PDP), 76.03% area-delay-product (ADP), and 84.8% power-area-product (PAP) as compared to the conventional Wallace multiplier. The ACMLC and CAC-based multiplier also achieves an ER of ‘1’, but with a higher MRED of \(64.9\times {10}^{-3}\) and NMED of \(24.25\times {10}^{-3}\) , reflecting moderate approximation accuracy of 93.51%. This makes it highly energy-efficient and well-suited for Error-Resilient applications, such as image smoothing, sharpening, fusion, and blending, which are used to produce high-quality visual images.