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<p>Multi-stage biopotential analog front-ends (AFE), targeting wireless continuous electrocardiogram (ECG) monitors, with large output swings suffer from poor signal-to-distortion ratio (SDR) performance. Reducing the number of amplification stages limits the output swing available for digitization, especially in the case of low-amplitude physiological signals, thereby negating the use of low- resolution quantizers. This paper presents the viability of scaling the reference voltage of the 1-bit digital-to-analog converter (DAC) in Σ∆ modulator to reduce the quantization noise, hence improving the signal-to-noise ratio (SNR) performance. A qualitative and quantitative analysis of the expected SNR performance enhancement, followed by a thorough verification using a SIMULINK-based model of a second-order cascade-of-integrators with distributed feedback (CIFB) Σ∆ modulator, qualifies the idea for CMOS implementation. The proposed technique utilizes an opamp-shared switched-capacitor topology and an enhanced recyclic folded cascode (ERFC) differential operational transconductance amplifier (OTA), with inherent common-mode feedback (CMFB), while ensuring low power dissipation. An effective number of bits (ENOB) around 11-bits is obtained, for a 200 mV<sub>p−p</sub> input swing, from the parasitic extracted simulation. The implemented design occupies an area of 0.72 mm<sup>2</sup> and consumes 1.4&#xa0;µW from a 1.8&#xa0;V supply. The Figure-of-Merit (FoM) of this design is 1.2 pJ/conv. The intended design is fabricated in a UMC 180&#xa0;nm CMOS technology and the chip measurements show a resolution of 6.5-bits. Finally, the standard PanTompkins ECG detection algorithm run on 6-bit MIT-BIH database ratifies the adequacy of the obtained resolution from the fabricated Σ∆ modulator for R-peak detection.</p>

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Utilizing Reference Voltage Scaling in ΣΔ ADC with Limited Input Dynamic Range Intended for Continuous Ambulatory Heartbeat Detection

  • 期刊论文

  • 发表日期：

    2025年9月4日

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  • Pankaj Kumar Jha,
  • Pravanjan Patra,
  • Vishnuvardhan Gundlapalle,
  • Ashudeb Dutta,
  • Amit Acharyya,
  • Sudarshan Vadnala

摘要

Multi-stage biopotential analog front-ends (AFE), targeting wireless continuous electrocardiogram (ECG) monitors, with large output swings suffer from poor signal-to-distortion ratio (SDR) performance. Reducing the number of amplification stages limits the output swing available for digitization, especially in the case of low-amplitude physiological signals, thereby negating the use of low- resolution quantizers. This paper presents the viability of scaling the reference voltage of the 1-bit digital-to-analog converter (DAC) in Σ∆ modulator to reduce the quantization noise, hence improving the signal-to-noise ratio (SNR) performance. A qualitative and quantitative analysis of the expected SNR performance enhancement, followed by a thorough verification using a SIMULINK-based model of a second-order cascade-of-integrators with distributed feedback (CIFB) Σ∆ modulator, qualifies the idea for CMOS implementation. The proposed technique utilizes an opamp-shared switched-capacitor topology and an enhanced recyclic folded cascode (ERFC) differential operational transconductance amplifier (OTA), with inherent common-mode feedback (CMFB), while ensuring low power dissipation. An effective number of bits (ENOB) around 11-bits is obtained, for a 200 mVp−p input swing, from the parasitic extracted simulation. The implemented design occupies an area of 0.72 mm2 and consumes 1.4 µW from a 1.8 V supply. The Figure-of-Merit (FoM) of this design is 1.2 pJ/conv. The intended design is fabricated in a UMC 180 nm CMOS technology and the chip measurements show a resolution of 6.5-bits. Finally, the standard PanTompkins ECG detection algorithm run on 6-bit MIT-BIH database ratifies the adequacy of the obtained resolution from the fabricated Σ∆ modulator for R-peak detection.