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<p>This paper presents a novel VLSI digital design and implementation of a proposed approximate <i>n</i>-bit adder. The adder is integrated into a Gaussian filter, which is implemented on the ASIC platform. The research findings show that the area, power, and delay results of the Approximate Gaussian Filter Chip(AGFC) are encouraging and found to be the least, indicating our results are the best after comparing our results with the state-of-the-art recent similar research literature. The entire hardware ASIC design has been implemented on Synopsys EDA tools using SAED-90nm technology. The software implementation for the performance metrics of the proposed AGFC has been implemented on MATLAB R2024b version. The results for MED, PSNR, MSE, and SSIM surpass those of the other compared articles, demonstrating superior performance among the referenced papers. None of the articles implemented the entire Gaussian filter using the approximate adder proposed in this paper. All other papers have implemented only their proposed approximate adder. This paper used the approximate adders implemented by other authors and implemented the 2D Gaussian filter, as well as our proposed approximate adder, and implemented the same 2D Gaussian filter. Our Approximate adder implementation of the Gaussian filter obtained the best results reported among all. When implemented within the Gaussian filter architecture, the AGFC achieved a 24.81% area reduction, 18.82% power reduction, and 49.72% delay improvement compared to the accurate Gaussian filter. Additionally, AGFC preserved high image quality, yielding a Mean Square Error (MSE) of 10.7834, Peak Signal-to-Noise Ratio (PSNR) of 43.84 dB, and Structural Similarity Index (SSIM) of 0.993. These results demonstrate that the proposed design offers a superior trade-off between hardware efficiency and output quality.</p>

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ASIC Design and Implementation of Fast 2D Gaussian Filter Chip Using Approximate Computing

  • 期刊论文

  • 发表日期：

    2025年9月6日

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  • Utsab Dhara,
  • Subhrajyoti Choudhury,
  • Sudip Ghosh,
  • Hafizur Rahaman

摘要

This paper presents a novel VLSI digital design and implementation of a proposed approximate n-bit adder. The adder is integrated into a Gaussian filter, which is implemented on the ASIC platform. The research findings show that the area, power, and delay results of the Approximate Gaussian Filter Chip(AGFC) are encouraging and found to be the least, indicating our results are the best after comparing our results with the state-of-the-art recent similar research literature. The entire hardware ASIC design has been implemented on Synopsys EDA tools using SAED-90nm technology. The software implementation for the performance metrics of the proposed AGFC has been implemented on MATLAB R2024b version. The results for MED, PSNR, MSE, and SSIM surpass those of the other compared articles, demonstrating superior performance among the referenced papers. None of the articles implemented the entire Gaussian filter using the approximate adder proposed in this paper. All other papers have implemented only their proposed approximate adder. This paper used the approximate adders implemented by other authors and implemented the 2D Gaussian filter, as well as our proposed approximate adder, and implemented the same 2D Gaussian filter. Our Approximate adder implementation of the Gaussian filter obtained the best results reported among all. When implemented within the Gaussian filter architecture, the AGFC achieved a 24.81% area reduction, 18.82% power reduction, and 49.72% delay improvement compared to the accurate Gaussian filter. Additionally, AGFC preserved high image quality, yielding a Mean Square Error (MSE) of 10.7834, Peak Signal-to-Noise Ratio (PSNR) of 43.84 dB, and Structural Similarity Index (SSIM) of 0.993. These results demonstrate that the proposed design offers a superior trade-off between hardware efficiency and output quality.