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<p>This paper presents a fully integrated radio frequency front-end (RFFE) for ultra-wideband (UWB) receivers. The RFFE is a direct-RF receiver comprising a low-noise amplifier (LNA), an active balanced-to-unbalanced (BALUN), and three-stage variable-gain amplifiers (VGA). Instead of using complex matching networks with multiple inductors and capacitors, the common-drain (CD) structure is adopted as the feedback loop for LNA and the bias circuit for the main amplifying transistor to improve the NF and save the chip area. A pair of cross-coupling capacitors (CCC) is introduced in the BALUN to minimize the gain and phase errors. This work proposes a new method to realize variable gain by adjusting the current ratio of the main and secondary branches while maintaining a certain total current. The chip is fabricated in 65&#xa0;nm CMOS with an occupied core module area of 0.19&#xa0;mm<sup>2</sup>. The peak DC power consumption of the RFFE is 76.5&#xa0;mW with a 1.8&#xa0;V supply voltage. In the 3.1–10.6&#xa0;GHz frequency band, the key indicators S11, S21, noise figure (NF), input third-order intercept point (IIP3), gain error, and phase error of the RFFE are below −&#xa0;7.56&#xa0;dB, 20.25–48.70&#xa0;dB, 4.43&#xa0;dB, and −&#xa0;28.95&#xa0;dBm, −&#xa0;0.503 to 0.191&#xa0;dB, and −&#xa0;1.236° to 0.952°, respectively. The proposed UWB RFFE architecture measurements exhibit good matching performance, a high and flat gain, low NF, and low mismatch with a small chip area.</p>

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A 0.19 mm2 3.1–10.6 GHz RF Front-End with High Gain and High Dynamic Tunable Range for UWB Systems in 65 nm CMOS

  • 期刊论文

  • 发表日期：

    2025年9月4日

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  • Yuyang Liu,
  • Peng Luo,
  • Maliang Liu,
  • Yintang Yang

摘要

This paper presents a fully integrated radio frequency front-end (RFFE) for ultra-wideband (UWB) receivers. The RFFE is a direct-RF receiver comprising a low-noise amplifier (LNA), an active balanced-to-unbalanced (BALUN), and three-stage variable-gain amplifiers (VGA). Instead of using complex matching networks with multiple inductors and capacitors, the common-drain (CD) structure is adopted as the feedback loop for LNA and the bias circuit for the main amplifying transistor to improve the NF and save the chip area. A pair of cross-coupling capacitors (CCC) is introduced in the BALUN to minimize the gain and phase errors. This work proposes a new method to realize variable gain by adjusting the current ratio of the main and secondary branches while maintaining a certain total current. The chip is fabricated in 65 nm CMOS with an occupied core module area of 0.19 mm2. The peak DC power consumption of the RFFE is 76.5 mW with a 1.8 V supply voltage. In the 3.1–10.6 GHz frequency band, the key indicators S11, S21, noise figure (NF), input third-order intercept point (IIP3), gain error, and phase error of the RFFE are below − 7.56 dB, 20.25–48.70 dB, 4.43 dB, and − 28.95 dBm, − 0.503 to 0.191 dB, and − 1.236° to 0.952°, respectively. The proposed UWB RFFE architecture measurements exhibit good matching performance, a high and flat gain, low NF, and low mismatch with a small chip area.