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<p>As CMOS technology scales down, the supply voltage is reduced to prevent device failure from high electric fields. Although this decreases dynamic power dissipation, it also slows down transistor switching speeds. To compensate, threshold voltages are lowered, which causes an exponential increase in sub-threshold leakage current. Power gating (PG), also known as Multi-threshold CMOS, effectively mitigates standby leakage power during periods of extended inactivity. However, conventional and multi-mode PG techniques are highly susceptible to process variations, which complicates manufacturability and limits the application to multiple power-off modes. Additionally, the substantial inductive noise (Ldi/dt) generated by PG can disrupt the normal operation of adjacent circuits. Our proposed multi-mode PG structure addresses these challenges by gradually turning the sleep transistor on and off, resulting in a current profile with reduced Ldi/dt. The optimized design for 90nm CMOS demonstrates superior power reduction compared to previous methods. Extensive analysis and PVT-aware simulation results along with testing on ISCAS’89 benchmark circuits validate the effectiveness of our proposed configuration.</p>

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Multi-mode Power Gating to Reduce Current Ramp of Logic Circuit

  • 期刊论文

  • 发表日期：

    2025年7月31日

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  • Vijay Pratap Yadav,
  • Vipin Kumar Singh,
  • Sanjeev Kumar Metya,
  • Alak Majumder

摘要

As CMOS technology scales down, the supply voltage is reduced to prevent device failure from high electric fields. Although this decreases dynamic power dissipation, it also slows down transistor switching speeds. To compensate, threshold voltages are lowered, which causes an exponential increase in sub-threshold leakage current. Power gating (PG), also known as Multi-threshold CMOS, effectively mitigates standby leakage power during periods of extended inactivity. However, conventional and multi-mode PG techniques are highly susceptible to process variations, which complicates manufacturability and limits the application to multiple power-off modes. Additionally, the substantial inductive noise (Ldi/dt) generated by PG can disrupt the normal operation of adjacent circuits. Our proposed multi-mode PG structure addresses these challenges by gradually turning the sleep transistor on and off, resulting in a current profile with reduced Ldi/dt. The optimized design for 90nm CMOS demonstrates superior power reduction compared to previous methods. Extensive analysis and PVT-aware simulation results along with testing on ISCAS’89 benchmark circuits validate the effectiveness of our proposed configuration.