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<p>Approximate computing harnesses the fact that certain applications can tolerate loss of precision and hence accuracy can be sacrificed for gaining hardware performance. In this paper, Approximate Restoring array-based Log Divider (ARLD) that utilizes Restoring array architecture and Log divider algorithm is proposed. In ARLD, the first approximation is introduced by replacing the least rows of restoring divider with a log divider for the Least Significant quotient bits. To maximize energy efficiency, the exact restoring divider cells are further approximated and this approximation was implemented for different replacement schemes. Based on these two approximations, various divider architecture designs are implemented and analyzed to identify the best energy efficiency and accuracy tradeoff. Accuracy performance evaluation shows that proposed dividers with a properly chosen value of approximation factor, perform better than existing dividers in terms of both hardware efficiency and accuracy. Synthesized in 180&#xa0;nm CMOS process, the proposed divider reports a maximum of 88% reduction in power and up to 80% improvement in critical path delay when compared to exact restoring dividers. The proposed dividers with optimal approximation factors show NMED in the range of 0.01 to 0.02. The simulation results shows that the Relative Error Distribution lies well within 5–10%, thus the approximated output remains close to exact output showing very less deviation. To prove that the reduction in accuracy does not degrade the performance in real time, two image processing applications, such as, change detection and foreground extraction of an image were considered and simulation results were promising.</p>

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Design and Analysis of a High-Speed Approximate Restoring Array Based Log Divider (ARLD)

  • 期刊论文

  • 发表日期：

    2025年9月7日

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  • P. Gowtham,
  • A. Anita Angeline,
  • P. Sasipriya

摘要

Approximate computing harnesses the fact that certain applications can tolerate loss of precision and hence accuracy can be sacrificed for gaining hardware performance. In this paper, Approximate Restoring array-based Log Divider (ARLD) that utilizes Restoring array architecture and Log divider algorithm is proposed. In ARLD, the first approximation is introduced by replacing the least rows of restoring divider with a log divider for the Least Significant quotient bits. To maximize energy efficiency, the exact restoring divider cells are further approximated and this approximation was implemented for different replacement schemes. Based on these two approximations, various divider architecture designs are implemented and analyzed to identify the best energy efficiency and accuracy tradeoff. Accuracy performance evaluation shows that proposed dividers with a properly chosen value of approximation factor, perform better than existing dividers in terms of both hardware efficiency and accuracy. Synthesized in 180 nm CMOS process, the proposed divider reports a maximum of 88% reduction in power and up to 80% improvement in critical path delay when compared to exact restoring dividers. The proposed dividers with optimal approximation factors show NMED in the range of 0.01 to 0.02. The simulation results shows that the Relative Error Distribution lies well within 5–10%, thus the approximated output remains close to exact output showing very less deviation. To prove that the reduction in accuracy does not degrade the performance in real time, two image processing applications, such as, change detection and foreground extraction of an image were considered and simulation results were promising.