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<p>Many error resilient applications in the area of machine learning, communication systems, image &amp; signal processing require approximate arithmetic circuits optimized for speed, power and area. Approximate circuits exploits a trade-off of accuracy in computation versus performance and power. However, required Fast accuracy varies according to applications. In this article, extremely Fast Accuracy Reconfigurable Adder (FARA) has been proposed which combines the advantages of RAP-CLA and SARA. When compared to SARA, FARA showcases for an improvement of 7 to 9 times across all accuracy metrics. This is achieved with roughly a penalty of 10% in delay, area and power in comparison to SARA. In comparison to RAP-CLA, FARA shows 50% improvement in ER with almost similar values of other error parameters with slight overhead in terms of delay and area. The proposed adder is combined with a novel approach of recursive addition of partial products in fast accurate recursive approximate multiplier that can drastically cut down on the area overhead associated with standard recursive multipliers. The error analysis of 32-bit multiplier has shown 27 % improvement in Error Rate, 48 % improvement in Error Distance, 50 % improvement in Hamming Distance Parameter. In comparison to traditional precise multipliers, the design provides a speedup of over 30% while maintaining exceptionally high accuracy regardless of input size. Although there is a slight area overhead associated with accuracy-configurable architecture, it provides us with the flexibility to get an exact output when necessary. This is just another distinctive aspect of our design.</p>

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Design and Analysis of an Accuracy Configurable Fast Approximate Recursive Multiplier

  • 期刊论文

  • 发表日期：

    2025年7月29日

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  • Viraj Joshi,
  • Archit Agarwal,
  • Pravin Mane

摘要

Many error resilient applications in the area of machine learning, communication systems, image & signal processing require approximate arithmetic circuits optimized for speed, power and area. Approximate circuits exploits a trade-off of accuracy in computation versus performance and power. However, required Fast accuracy varies according to applications. In this article, extremely Fast Accuracy Reconfigurable Adder (FARA) has been proposed which combines the advantages of RAP-CLA and SARA. When compared to SARA, FARA showcases for an improvement of 7 to 9 times across all accuracy metrics. This is achieved with roughly a penalty of 10% in delay, area and power in comparison to SARA. In comparison to RAP-CLA, FARA shows 50% improvement in ER with almost similar values of other error parameters with slight overhead in terms of delay and area. The proposed adder is combined with a novel approach of recursive addition of partial products in fast accurate recursive approximate multiplier that can drastically cut down on the area overhead associated with standard recursive multipliers. The error analysis of 32-bit multiplier has shown 27 % improvement in Error Rate, 48 % improvement in Error Distance, 50 % improvement in Hamming Distance Parameter. In comparison to traditional precise multipliers, the design provides a speedup of over 30% while maintaining exceptionally high accuracy regardless of input size. Although there is a slight area overhead associated with accuracy-configurable architecture, it provides us with the flexibility to get an exact output when necessary. This is just another distinctive aspect of our design.