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<p>Design of multistage structures using hybrid full adder (HFA) poses a unique challenge that requires careful consideration and innovative solutions. By harnessing the capabilities of full adders (FAs), complex digital architecture can be achieved with optimal performance. High driving capability and full swing output are crucial for designing cascade structures in digital circuits. It ensures signal integrity, faster operation, precise signal levels, and power efficiency. The HFAs with transmission gate (TG) are crucial in developing multistage structures. The TG offer strong drive strength, allowing the FA to drive to subsequent stages without significant signal degradation. This article proposes a high-speed, low-power HFA cell that delivers full-swing outputs, while offering minimized delay performance. In addition, the 4-bit, 8-bit, 16-bit ripple carry adder circuit utilizing the proposed HFA exhibits substantial improvements, achieving efficiency gains ranging from 3.11 to 49.17% over conventional designs documented in the literature. These results highlight the efficacy of the HFA cell with TG in enhancing the performance of multistage digital circuits.</p>

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A Novel Approach: Hybrid Full Adder Design Tailored for Multistage Architecture

  • 期刊论文

  • 发表日期：

    2025年10月3日

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  • Dinesh Kumar,
  • P. Karuppanan

摘要

Design of multistage structures using hybrid full adder (HFA) poses a unique challenge that requires careful consideration and innovative solutions. By harnessing the capabilities of full adders (FAs), complex digital architecture can be achieved with optimal performance. High driving capability and full swing output are crucial for designing cascade structures in digital circuits. It ensures signal integrity, faster operation, precise signal levels, and power efficiency. The HFAs with transmission gate (TG) are crucial in developing multistage structures. The TG offer strong drive strength, allowing the FA to drive to subsequent stages without significant signal degradation. This article proposes a high-speed, low-power HFA cell that delivers full-swing outputs, while offering minimized delay performance. In addition, the 4-bit, 8-bit, 16-bit ripple carry adder circuit utilizing the proposed HFA exhibits substantial improvements, achieving efficiency gains ranging from 3.11 to 49.17% over conventional designs documented in the literature. These results highlight the efficacy of the HFA cell with TG in enhancing the performance of multistage digital circuits.