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<p>Versatile Video Coding (VVC/H.266) is a modern video coding standard developed for a variety of next-generation media applications. It is a growing alternative to the widely used High-Efficiency Video Coding (HEVC/H.265), which has been proven to increase encoding capacity while maintaining subjective visual quality. However, these advancements lead to an increase in the hardware’s complexity. In this paper, a low-cost VVC (LC-VVC) standard is proposed with optimized motion estimation and transform block. The VVC transform block consists of Multiple Transform Selection (MTS) and Low Frequency Non-Separable Transform (LFNST). The use of several trigonometric components (DCT/DSTs) is projected to increase the complexity of VVC software decoders compared to HEVC decoders. To address this issue, a new arithmetic unit optimized Transform blocks (AUO-TB) are proposed for the VVC standard, which uses a two-stage ultrafast pipelined booth multiplier (2SUP-BM) in a pipelined architecture. In addition, the VVC hardware’s motion estimation block uses a fully parallel arithmetic unit optimized for full search motion estimation with SAD (AUO-FSME-SAD) with a three-operand adder to reduce hardware footprint. According to the simulation results, the proposed MTS uses just 162.2&#xa0;k gates and consumes 45.98 mW of power. The proposed idea is a feasible option compared to other encoders from scratch due to its decreased logic resources and promising coding performance.</p>

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LC-VVC: Design of Low-Cost Versatile Video Coding Standard Based on Optimized Motion Estimation and Transform Blocks

  • 期刊论文

  • 发表日期：

    2025年7月9日

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  • L. Vigneash,
  • H. Azath,
  • Lakshmi R. Nair,
  • Kamalraj Subramaniam

摘要

Versatile Video Coding (VVC/H.266) is a modern video coding standard developed for a variety of next-generation media applications. It is a growing alternative to the widely used High-Efficiency Video Coding (HEVC/H.265), which has been proven to increase encoding capacity while maintaining subjective visual quality. However, these advancements lead to an increase in the hardware’s complexity. In this paper, a low-cost VVC (LC-VVC) standard is proposed with optimized motion estimation and transform block. The VVC transform block consists of Multiple Transform Selection (MTS) and Low Frequency Non-Separable Transform (LFNST). The use of several trigonometric components (DCT/DSTs) is projected to increase the complexity of VVC software decoders compared to HEVC decoders. To address this issue, a new arithmetic unit optimized Transform blocks (AUO-TB) are proposed for the VVC standard, which uses a two-stage ultrafast pipelined booth multiplier (2SUP-BM) in a pipelined architecture. In addition, the VVC hardware’s motion estimation block uses a fully parallel arithmetic unit optimized for full search motion estimation with SAD (AUO-FSME-SAD) with a three-operand adder to reduce hardware footprint. According to the simulation results, the proposed MTS uses just 162.2 k gates and consumes 45.98 mW of power. The proposed idea is a feasible option compared to other encoders from scratch due to its decreased logic resources and promising coding performance.