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<p>A novel pull–push output-capacitorless low-dropout regulator (OCL-LDO) based on Flipped Voltage Follower (FVF) embedded Super Source Follower (SSF) and high-pass network (HPN) is introduced, which is designed for the power management of system-on-chip (SoC). The innovative pull–push architecture significantly alleviates the slew rate constraint encountered at the gate of the power transistor. The post-layout simulation results, validated through rigorous 180&#xa0;nm CMOS manufacturing procedures, underscore the remarkable stability exhibited by the proposed LDO regulator over an extensive loading current spectrum, spanning from 100&#xa0;μA to 50&#xa0;mA. This achievement is accomplished with a minimal Miller compensation capacitance of merely 1.8 pF, emphasizing the efficiency and compactness of the design. The circuitry functions with a low quiescent current of 37.8 μA, sourced from a single 1.5&#xa0;V supply. The LDO regulator stands out with a dropout voltage of 300&#xa0;mV, empowering it to provide up to 50&#xa0;mA of load current, ensuring efficient performance across a broad range of applications. The simulation outcomes reveal that, during rapid load current transitions from 100&#xa0;μA to 50&#xa0;mA within a 300&#xa0;ns edge time, the undershoot voltage is effectively contained at a mere 68.2&#xa0;mV, even under the condition of a minimal 1 pF capacitive load. Notably, the system swiftly recovers to its equilibrium state following this abrupt change, with a recovery time of approximately 1&#xa0;μs, showcasing robust dynamic performance.</p>

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A Fast Response FVF-Based Output-Capacitorless LDO with Super Source Follower and High-Pass Network Integration

  • 期刊论文

  • 发表日期：

    2025年6月2日

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  • Hang Shu,
  • Pengfei Liao,
  • Haiqing Peng,
  • Wensuo Chen

摘要

A novel pull–push output-capacitorless low-dropout regulator (OCL-LDO) based on Flipped Voltage Follower (FVF) embedded Super Source Follower (SSF) and high-pass network (HPN) is introduced, which is designed for the power management of system-on-chip (SoC). The innovative pull–push architecture significantly alleviates the slew rate constraint encountered at the gate of the power transistor. The post-layout simulation results, validated through rigorous 180 nm CMOS manufacturing procedures, underscore the remarkable stability exhibited by the proposed LDO regulator over an extensive loading current spectrum, spanning from 100 μA to 50 mA. This achievement is accomplished with a minimal Miller compensation capacitance of merely 1.8 pF, emphasizing the efficiency and compactness of the design. The circuitry functions with a low quiescent current of 37.8 μA, sourced from a single 1.5 V supply. The LDO regulator stands out with a dropout voltage of 300 mV, empowering it to provide up to 50 mA of load current, ensuring efficient performance across a broad range of applications. The simulation outcomes reveal that, during rapid load current transitions from 100 μA to 50 mA within a 300 ns edge time, the undershoot voltage is effectively contained at a mere 68.2 mV, even under the condition of a minimal 1 pF capacitive load. Notably, the system swiftly recovers to its equilibrium state following this abrupt change, with a recovery time of approximately 1 μs, showcasing robust dynamic performance.