<p>With the increasing adoption of Edge AI devices, designing efficient machine learning systems requires optimizing both computational models and sensor architectures. While, Binarized Neural Networks (BNNs) offer a promising solution by significantly reducing memory and computational demands, this work introduces a co-design methodology that integrates sparsity with reduced ADC precision during acquisition at the sensor level to enhance efficiency. The approach involves edge extraction within images in the analog domain, followed by selective quantization level at the ADC, reducing redundant information before digital processing. The impact of varying sparsity levels, defined by [4, 3, 2, 1] conversion bits, is evaluated on BNN models, including AlexNet, VGG, ResNet, SqueezeNet, and MobileNet. Experimental results on CIFAR-10 and STL-10 datasets demonstrate that reducing ADC precision from 4-bit to 1-bit leads to an approximate 10% accuracy drop (from <InlineEquation ID="IEq1"> <EquationSource Format="TEX">$65.27\%$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>65.27</mn> <mo>%</mo> </mrow> </math></EquationSource> </InlineEquation> to <InlineEquation ID="IEq2"> <EquationSource Format="TEX">$54.85\%$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>54.85</mn> <mo>%</mo> </mrow> </math></EquationSource> </InlineEquation> in AlexNet on CIFAR-10), while achieving significant reductions in memory and power consumption. Specifically, the proposed approach reduces ADC power by approximately <InlineEquation ID="IEq3"> <EquationSource Format="TEX">$94\%$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>94</mn> <mo>%</mo> </mrow> </math></EquationSource> </InlineEquation>, lowering energy requirements from 15.61 mW to 0.86 mW for a <InlineEquation ID="IEq4"> <EquationSource Format="TEX">$32 \times 32$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>32</mn> <mo>×</mo> <mn>32</mn> </mrow> </math></EquationSource> </InlineEquation> pixel array. These results validate the effectiveness of sensor-driven sparsity in enabling energy-efficient AI inference, highlighting its potential for real-world edge computing applications.</p>

Efficient Edge-AI with Binarized Neural Networks and CMOS Image Sensors: A Sparsity-Driven Approach

期刊论文
发表日期：

2025年5月14日

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Wilfred Kisku,
Amandeep Kaur,
Deepak Mishra

摘要

With the increasing adoption of Edge AI devices, designing efficient machine learning systems requires optimizing both computational models and sensor architectures. While, Binarized Neural Networks (BNNs) offer a promising solution by significantly reducing memory and computational demands, this work introduces a co-design methodology that integrates sparsity with reduced ADC precision during acquisition at the sensor level to enhance efficiency. The approach involves edge extraction within images in the analog domain, followed by selective quantization level at the ADC, reducing redundant information before digital processing. The impact of varying sparsity levels, defined by [4, 3, 2, 1] conversion bits, is evaluated on BNN models, including AlexNet, VGG, ResNet, SqueezeNet, and MobileNet. Experimental results on CIFAR-10 and STL-10 datasets demonstrate that reducing ADC precision from 4-bit to 1-bit leads to an approximate 10% accuracy drop (from $65.27\%$ $65.27 %$ to $54.85\%$ $54.85 %$ in AlexNet on CIFAR-10), while achieving significant reductions in memory and power consumption. Specifically, the proposed approach reduces ADC power by approximately $94\%$ $94 %$ , lowering energy requirements from 15.61 mW to 0.86 mW for a $32 \times 32$ $32 \times 32$ pixel array. These results validate the effectiveness of sensor-driven sparsity in enabling energy-efficient AI inference, highlighting its potential for real-world edge computing applications.