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<p>Approximate computing (AC) is commonly employed in image processing tasks where some degree of fault tolerance is satisfactory, ordering faster circuit performance over complete accuracy. Efforts are often directed towards enhancing the efficiency of the binary multiplier, an critical but power-hungry operation, to reduce complexity. Inexact recursive multipliers utilize imprecise building blocks to achieve their final multiplication output, which are offering low-power alternatives. To assess their performance, proposed multipliers and existing designs are synthesized using a 90&#xa0;nm CMOS technology. This study introduces two innovative 4-bit Inexact Multipliers (IMs) utilizing carry manipulation, scalable to 8-bit, 16-bit, and 32-bit configurations with varying levels of error and performance. Compared to precise 8-bit multipliers, the most efficient design presented here consumes 46% less power while maintaining 99% higher accuracy than the less power-efficient compared to existing IMs. Th image-processing applications, offering competitive error rates and reduced power dissipation compared to current prior designs.</p>

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Performance Analysis of Low Power Inexact Recursive Multipliers for Image Processing Applications

  • 期刊论文

  • 发表日期：

    2025年4月26日

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  • S. Harichandra Prasad,
  • K. Kumar

摘要

Approximate computing (AC) is commonly employed in image processing tasks where some degree of fault tolerance is satisfactory, ordering faster circuit performance over complete accuracy. Efforts are often directed towards enhancing the efficiency of the binary multiplier, an critical but power-hungry operation, to reduce complexity. Inexact recursive multipliers utilize imprecise building blocks to achieve their final multiplication output, which are offering low-power alternatives. To assess their performance, proposed multipliers and existing designs are synthesized using a 90 nm CMOS technology. This study introduces two innovative 4-bit Inexact Multipliers (IMs) utilizing carry manipulation, scalable to 8-bit, 16-bit, and 32-bit configurations with varying levels of error and performance. Compared to precise 8-bit multipliers, the most efficient design presented here consumes 46% less power while maintaining 99% higher accuracy than the less power-efficient compared to existing IMs. Th image-processing applications, offering competitive error rates and reduced power dissipation compared to current prior designs.